ISE Design Suite
Map Properties
The following properties are available for the Map and Implement Design processes for FPGA designs.
  • Perform Timing-Driven Packing and Placement (Advanced) (Spartan«-3, Spartan-3A, Spartan-3E, and Virtex«-4 devices only)
    Specifies whether or not to give priority to timing critical paths during packing in the Map process. User-generated timing constraints are used to drive the packing and placement operations. The timing constraints are generally specified in the User Constraints File (UCF) and are annotated onto the design during the Translate process. At the completion of the process, the result is a completely placed design, and the design is ready for routing.
    If Timing-Driven Packing and Placement is selected in the absence of user timing constraints, the tools automatically generate and dynamically adjust timing constraints for all internal clocks. This feature is referred to as Performance Evaluation Mode. This mode allows the clock performance for all clocks in the design to be evaluated in one pass. The performance achieved by this mode is not necessarily the best possible performance each clock can achieve. Instead it is a balance of performance between all clocks in the design.
    By default, this property is set to False (checkbox is blank).
  • Map Effort Level (Advanced) (Spartan-3, Spartan-3A, Spartan-3E, and Virtex-4 devices only)
    NoteáThis property is only available when Perform Timing-Driven Packing and Placement is set to True (checkbox is checked).
    Specifies the effort level you want to apply to the Map process. The effort level controls the amount of time used for packing and placement by selecting a more or less CPU-intensive algorithm for placement. Select an option from the drop-down list.
    • Standard
      Gives the fastest runtime with the lowest mapping effort. This setting is appropriate for a less complex design.
    • High
      Gives the longest runtime with the best mapping results. This setting is appropriate for a more complex design.
    By default, this property is set to Standard.
  • Extra Effort (Advanced) (Spartan-3, Spartan-3A, Spartan-3E, and Virtex-4 devices only)
    NoteáThis property is only available when the Map Effort Level is set to High.
    Specifies whether Map spends additional runtime in an effort to meet difficult timing constraints. Select an option from the drop-down list.
    • None
      No extra effort is applied.
    • Normal
      Runs until timing constraints are met unless they are found to be impossible to meet. This option focuses on meeting timing constraints.
    • Continue on Impossible
      Continues working to improve timing until no more progress is made, even if timing constraints are impossible. This option focuses on getting close to meeting timing constraints.
    By default, this property is set to None.
  • Placer Effort Level (Advanced) (Spartan-6, Virtex-5, Virtex-6, 7 series, and ZynqÖ devices only)
    Specifies the effort level to apply to the Map process. The effort level controls the amount of time used for packing and placement by selecting a more or less CPU-intensive algorithm for placement. Select an option from the drop-down list.
    • Standard
      Gives the fastest runtime with the lowest mapping effort. This setting is appropriate for a less complex design.
    • High
      Gives the longest runtime with the best mapping results. This setting is appropriate for a more complex design.
    By default, this property is set to High.
  • Placer Extra Effort (Advanced) (Spartan-6, Virtex-5, Virtex-6, 7 series, and Zynq devices only)
    NoteáThis property is only available if the Placer Effort Level is set to High.
    Specifies the extra effort level for timing-driven packing. Select an option from the drop-down list.
    • None
      No extra effort is applied.
    • Normal
      Runs until timing constraints are met unless they are found to be impossible to meet. This setting focuses on meeting timing constraints.
    • Continue on Impossible
      Continues working to improve timing until no more progress is made, even if timing constraints are impossible. This setting focuses on getting close to meeting timing constraints.
    By default, this property is set to None.
  • Starting Placer Cost Table (1 - 100) (Advanced)
    NoteáThis property is only available when the Perform Timing-Driven Packing and Placement property is set to True (checkbox is checked).
    Specifies a mapping initialization value with which to begin the map attempts. Each subsequent attempt is assigned an incremental value based on the mapping initialization value.
    By default, this property is set to 1.
  • Extra Cost Tables (Advanced) (Spartan-6, Virtex-6, 7 series, and Zynq devices only)
    Specifies cost tables for use with highly utilized designs. These cost tables can be used in conjunction with the Starting Placer Cost Table property.
    By default, this property is set to 0.
  • Combinatorial Logic Optimization (Advanced)
    NoteáThis property is only available when the Perform Timing-Driven Packing and Placement property is set to True (checkbox is checked).
    Specifies whether or not to run a process that revisits the combinatorial logic within a design to see if any improvements can be made that will improve the overall quality of results. Timing constraints and logic packing information are considered when this process is run. This property is part of the physical synthesis tools in the ISE« Design Suite.
    By default, this property is set to False (checkbox is blank), and this process is not run on the design.
  • Register Duplication (Advanced)
    NoteáThis property is available only when the Perform Timing-Driven Packing and Placement property is set True (checkbox is checked). Also note that when Global Optimization is enabled, Register Duplication is disabled.
    Specifies whether or not you want to replicate the registers to help control fanout.
    By default, this property is set to False (checkbox is blank), and register duplication is not performed during timing optimization and fanout control.
  • Register Ordering (Advanced) (Spartan-6, Virtex-6, 7 series, and Zynq devices only)
    Specifies whether to group registers that form a bus into ordered sequences of four or eight packed in a slice. The software determines whether a register forms a bus based on the register name. Select an option from the drop-down list.
    • Off
      Disables register ordering.
    • 4
      Uses four registers per slice.
      NoteáIf registers are sourced by a LUT, this setting uses eight registers per slice.
    • 8
      Uses eight registers per slice.
    By default, this property is set to 4.
  • Global Optimization (Advanced) (Spartan-6, Virtex-4, Virtex-5, and Virtex-6 devices only)
    Map performs global optimization routines on the fully assembled netlist before mapping the design. Global optimization includes logic remapping and trimming, logic and register replication and optimization, and logic replacement of tristates. These routines extend the runtime for Map, because extra processing occurs. Select an option from the drop-down list.
    • Off
      Disables optimization.
      NoteáWhen using Formal Verification flows, the recommended setting is Off.
    • Speed
      Optimizes logic to improve performance.
    • Area
      Optimizes logic to reduce area utilization.
      NoteáThis option is not available for Virtex-4 devices.
    • Power
      Optimizes logic to reduce dynamic power consumption. If you select this option, you can also specify a VCD or SAIF file using the Power Activity File property to guide the optimizations and provide additional power reduction.
      NoteáThis option is not available for Virtex-4 devices.
    The default is Off.
    NoteáWhen running Global Optimization, you must set Trim Unconnected Signals and Replicate Logic to Allow Logic Level Reduction to True. Also note that when Global Optimization is enabled, Register Duplication is disabled.
  • Equivalent Register Removal (Advanced) (Spartan-6 ,Virtex-4, Virtex-5, and Virtex-6 devices only)
    NoteáThis property is only available when the Global Optimization property is enabled.
    When this property is set to True (checkbox is checked), any registers with redundant functionality are examined to see if their removal will increase clock frequencies.
    By default, this property is set to True (checkbox is checked).
  • Ignore User Timing Constraints
    Controls the use of timing constraints during placement. The primary method of specifying timing requirements is by entering them in the User Constraints File (UCF). If this property is set to False (checkbox is blank), Map packs and places in accordance with any timing constraints specified in the UCF file.
    If this property is set to True (checkbox is checked), timing constraints in the UCF are ignored when Map runs, and Map proceeds as follows:
    • For Virtex-4 devices, packing and placement runs without timing constraints. The Timing Mode property indicates Non Timing Driven mode.
    • For Virtex-5 devices, the setting of the Timing Mode property determines whether Map automatically generates timing constraints to control packing and placement or runs without timing constraints.
    By default, this property is set to False (checkbox is blank).
    NoteáFor detailed information on timing constraints, see the Constraints Guide (UG625).
  • Timing Mode
    NoteáThis property is only available when the Ignore User Timing Constraints property is set to True (checkbox is checked).
    Select an option from the drop-down list.
    • Non Timing Driven
      In this mode, timing constraints specified in the UCF are ignored, and packing and placement will run with no timing constraints. This selection makes the Map process run faster, but will not take into account timing constraints while generating the resulting output.
    • Performance Evaluation
      This setting triggers the "Performance Evaluation" mode. In this mode, timing constraints specified in the UCF file are ignored. Instead, timing constraints for all internal clocks are generated automatically and dynamically adjusted during Map to increase performance. This mode is used to evaluate realistic performance targets for the design.
      Performance Evaluation is described in the "MAP" chapter of the Command Line Tools User Guide (UG628).
      NoteáThis setting is available for Virtex-5 devices only.
    By default, this property is set to Performance Evaluation for Virtex-5 devices and to Non Timing Driven for all other devices.
  • Trim Unconnected Signals
    Specifies whether or not to trim unconnected components and nets from the design before mapping occurs. Leaving this option blank is useful for estimating the logic resources required for a design and for obtaining timing information on partially finished designs. When implementing an unfinished design, set this property to False (checkbox is blank) to map unconnected components and nets.
    By default, this property is set to True (checkbox is checked), and unconnected components and nets are trimmed.
  • Allow Logic Optimization Across Hierarchy (Advanced)
    When this property is set to True (checkbox is checked), Map ignores any Keep Hierarchy properties set for the Synthesize process and Map can perform optimizations across any hierarchical boundaries. This property is used to preserve the signals that span the hierarchical boundaries for the purpose of simulation. Better timing performance can be attained by performing such optimizations.
    By default, this property is set to False (checkbox is blank).
  • Optimization Strategy (Cover Mode) (Advanced) (Spartan-3, Spartan-3A, Spartan-3E, Virtex-4, and Virtex-5 devices only)
    Specifies the criteria used during the "cover" phase of Map. In the "cover" phase, Map assigns the logic to CLB function generators (LUTs). Select an option from the drop-down list.
    • Area
      Makes reducing the number of LUTs (and therefore the number of CLBs) the highest priority.
    • Speed
      Makes reducing the number of levels of LUTS (the number of LUTs a path passes through) the highest priority. This setting makes it easiest to achieve your timing constraints after the design is placed and routed. For most designs there is a small increase in the number of LUTs (compared to the area setting), and in some cases the increase may be large.
    • Balanced
      Balances two priorities; reducing the number of LUTs and reducing the number of levels of LUTs. The Balanced option produces results similar to the Speed setting but avoids the possibility of a large increase in the number of LUTs.
    • Off
      Disables optimization.
    By default, this property is set to Area.
  • Generate Detailed MAP Report
    Specifies whether or not to display a detailed report. A detailed Map Report displays redundant blocks that were removed and signals that were merged during the mapping process. It also displays expanded logic, signal cross-references, and symbol cross-references. For Spartan-6, Virtex-5, Virtex-6, and 7 series devices, the detailed report includes a detailed list of control sets.
    By default, this property is set to False (checkbox is blank), and a detailed Map Report is not generated.
  • Use RLOC Constraints (Advanced)
    Specifies whether or not to use the RLOC information that contains the relative placement of one CLB to another. Select an option from the drop-down list.
    • Yes
      Map uses the RLOC information, including invalid information that could result in a Map process error.
    • No
      Map does not use the RLOC information.
    • For Packing Only
      Map uses the RLOC information only during packing.
    By default, this property is set to Yes.
  • Pack I/O Registers/Latches into IOBs
    Controls the packing of flip-flops or latches within an I/O cell. Normally, the mapper packs flip-flops or latches within an I/O cell only if such packing is specified by your design entry method. This option allows you to control packing after the design entry phase. Select an option from the drop-down list.
    • Off
      Select Off to pack flip-flops or latches as specified by your design entry method.
    • For Inputs Only
      Select Inputs Only to pack flip-flops or latches into input I/O cells.
    • For Outputs Only
      Select Outputs Only to pack flip-flops or latches into output I/O cells.
    • For Inputs and Outputs
      Select Inputs and Outputs to pack flip-flops or latches into both input and output I/O cells.
    By default, this property is set to Off for Virtex-5 devices and to For Inputs and Outputs for all other devices.
  • Maximum Compression (Advanced) (Spartan-6, Virtex-5, Virtex-6, 7 series, and Zynq devices only)
    When set to True (checkbox is checked), this option instructs Map to pack the design logic as densely as possible. This is done at the risk of negative Place and Route performance.
    By default, this property is set to False (checkbox is blank).
  • CLB Pack Factor Percentage (Advanced) (Spartan-3, Spartan-3A, Spartan-3E, and Virtex-4 devices only)
    NoteáThis property is only available when the Perform Timing-Driven Packing and Placement property is set False (checkbox is blank).
    Specifies how densely logic is partitioned using a percentage value. A higher percentage number results in lower density packing. A high CLB pack factor percentage can adversely affect Place and Route performance, resulting in higher delays and more unrouted nets.
    By default, this property is set to 100% which means that all CLBs in a target part are available for design logic.
  • LUT Combining (Advanced) (Spartan-6, Virtex-5, Virtex-6, 7 series, and Zynq devices only)
    LUT combining enables the merging of LUT pairs with common inputs into single dual-output 6-input LUTs in order to improve design area. This optimization process may reduce design speed. Select an option from the drop-down list.
    • Off
      Disables LUT combining.
    • Auto
      Map tries to make a trade-off between area and speed.
    • Area
      Map performs maximum LUT combining to provide as small an implementation as possible.
    By default, this property is set to Off.
  • Map Slice Logic into Unused Block RAMs (Advanced)
    Specifies whether or not MAP attempts to place LUTs and flip-flops into Block RAMs.
    By default, this property is set to False (checkbox is blank).
  • Power Reduction
    NoteáFor Spartan-3, Spartan-3A, Spartan-3E, and Virtex-4 devices, this property is only available when the Perform Timing-Driven Packing and Placement property is set to True (checkbox is checked).
    Power Reduction controls whether Map optimizes placement during timing-driven packing and placement to reduce the power consumed by the design. Select one of the following options.
    • Off/False (checkbox is blank)
      Disables power optimization.
    • On/True (checkbox is checked)
      Specifies the use of power optimization algorithms during placement to decrease capacitive loading on data and clocking nets to reduce overall dynamic power. The main trade-off with this option is additional runtime and modified placement which may result in slightly reduced performance.
    • High
      NoteáThis setting applies to Spartan-6, Virtex-6, and 7 series devices only.
      Specifies the use of intelligent clock gating algorithms that reduce overall switching to reduce dynamic power in the design. The main trade-off with this option is additional runtime, minor area increase, increased system memory requirements and additional logic in the data or control paths that can result in reduced performance. However, the power savings is generally more substantial than savings when you use the On setting.
    • Extra Effort
      NoteáThis setting applies to Spartan-6, Virtex-6, and 7 series devices only.
      Specifies the use of both On and High algorithms for the greatest reduction in dynamic power optimization. However, this selection generally has the largest impact on runtime, area, memory, and performance. This option is only recommended when you have adequate timing slack in the design and additional runtime and memory can be tolerated.
    By default, this property is set to Off/False (checkbox is blank).
  • Power Activity File
    NoteáThis property is only available if Power Reduction is set to On/True (checkbox is checked).
    Allows you to specify a simulation file, *.vcd or *.saif, to guide Map when it optimizes the design for power reduction. This file is the output of a simulation run on the design. For power reduction, Map uses this file to set frequencies and activity rates of internal signals, which are signals that are not inputs or outputs but internal to the design. For Spartan-6, Virtex-6, and 7 series devices, intelligent clock gating optimization is not affected by the power activity file.
    By default, this property is blank (no file name).
    NoteáSimulation is the most accurate method of determining the exact activity rates. Back-annotated post-Place and Route simulation provides the best data for determining activity rates since it most closely represents physical implementation.
  • Enable Multi-Threading (Advanced) (Spartan-6, Virtex-5, Virtex-6, 7 series, and Zynq devices only)
    Specifies whether to use multiple processors to enable multi-threading capabilities in both the Placer and the Router. When set to Off, one processor is used. When set to 2, two processors are used.
    By default, this property is set to Off.
  • Other Map Command Line Options (Advanced)
    Enter additional command line options. Separate multiple options with spaces. The options entered in this property appear first on the command line, before all other property options. Avoid setting duplicate property options.
    For more information about command line options, see the Command Line Tools User Guide (UG628).

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