Versal ACAP AI Engine Programming Environment User Guide (UG1076) - 2020.2 English

Document ID: UG1076
Release Date: 2020-11-24
Version: 2020.2 English

Revision History
Overview
Navigating Content by Design Process
AI Engine Architecture Overview
AI Engine Tile Architecture
Tools
Documentation
AI Engine Programming
Prepare the Kernels
Creating a Data Flow Graph (Including Kernels)
Recommended Project Directory Structure
Compiling and Running the Graph from the Command Line
Window and Streaming Data API
Data Access Mechanisms
Window-based Access
Synchronous Window Access
Asynchronous Window Access
Stream-based Access
Window Operations for Kernels
Window Data Types
Moving the Current Read/Write Position Forward
Moving the Current Read/Write Position Backward
Reading Data from an Input Window
Reading and Advancing an Input Window
Reading and Decrementing an Input Window
Writing Data to an Output Window
Writing and Advancing an Output Window
Stream Operations for Kernels
Stream Data Types
Reading and Advancing an Input Stream
Writing and Advancing an Output Stream
Using Streams in Parallel
Packet Stream Operations
Run-Time Graph Control API
Graph Execution Control
Run-Time Parameter Specification
Specifying Run-Time Data Parameters
Run-Time Parameter Update/Read Mechanisms
Parameter Update/Read using Graph APIs
Chained Updates Between AI Engine Kernels
Run-Time Graph Reconfiguration Using Control Parameters
Bypass Control Using Run-Time Parameters
Sharing Run-Time Parameters Across Multiple Kernels
Run-Time Parameter Support Summary
Specialized Graph Constructs
Look-up Tables
Stream FIFO Depth
Kernel Bypass
Explicit Packet Switching
Packet Switching Graph Constructs
Packet Switching and the AI Engine Simulator
Location Constraints
Buffer Allocation Control
C++ Kernel Class Support
C++ Template Support
AI Engine/Programmable Logic Integration
Model PL Kernels with C++
Programmable Logic Stream Operations
HLS Kernels Written in C/C++
Supported High-Level Synthesis Features in the AI Engine Compiler
Using High-Level Synthesis IP in Data Flow Graphs
Connecting High-Level Synthesis Kernels with Other Kernels in Data Flow Graphs
AXI4-Lite Interface and Control Protocols
Run-Time Parameter Support Summary for PL Kernel
Design Flow Using RTL Programmable Logic
Design Considerations for Graphs Containing Programmable Logic Kernels
PL Interface Tile Capabilities
AI Engine-to-PL Rate Matching
PL-to-PL Connections
AI Engine-PL Interface Performance
Using a Virtual Platform
Virtual Platform
FileIO Attributes
PLIO Attributes
GMIO Attributes
Programming Model for AI Engine–DDR Memory Connection
Programming Model for PL-DDR Memory Connection
Working in Hardware Flow
Compiling an AI Engine Graph Application
Setting up the Vitis Tool Environment
Inputs
Outputs
AI Engine Compiler Options
Mapper and Router Options
Viewing Compilation Results in the Vitis Analyzer
Simulating an AI Engine Graph Application
AI Engine System C Simulator
Simulator Options
Simulating Global Memory
Simulator Options for Hardware Emulation
Enabling Third-Party Simulators
x86 Functional Simulator (x86simulator)
Performance Analysis of AI Engine Graph Application
AI Engine Simulation-Based Performance Analysis
AI Engine Simulation-Based Value Change Dump
VCD File Generation
AI Engine Trace from VCD
Viewing the Run Summary in the Vitis Analyzer
Using Trace Compass to Visualize AI Engine Traces
Trace Views
Profiling the AI Engine
Run-Time Event API for Performance Profiling
Profiling Platform I/O Port Bandwidth
Profiling Graph Throughput
Profiling Graph Latency
Profiling using Performance Counters
AI Engine Heat Maps and Histograms
Profile Summary
Guidance Summary
Event Tracing in Hardware [Early Access]
Event Trace Build Flow
Running the Design in Hardware and Capturing Trace Data at Run Time
Viewing and Analyzing the Trace Data Using Vitis Analyzer
Using Multiple Event Trace Streams
Programming the PS Host Application
Host Programming on Linux
Controlling the AI Engine Graph with the ADF API
Controlling the PL Kernel with the XRT API
Controlling PL Kernels with the OpenCL API
Controlling the AI Engine Graph with the XRT API
Error Reporting Through the XRT API
AI Engine Error Events
Host Code Reference with ADF API and XRT API
Host Programming for Bare-metal Systems
Addressing Kernels in Bare-metal Applications
Integrating the Application Using the Vitis Tools Flow
Platforms
PL Kernels
Compiling PL Kernels
Clocking the PL Kernels
Linking the System
Compile the Embedded Application for the Cortex-A72 Processor
Packaging
Packaging the System
Building a Bare-metal System
Running the System
Deploying the System
Using the Vitis IDE
Creating the AI Engine Graph Project and Top-Level System Project
Importing Source Files
Vitis Tools Template Examples
Building the AI Engine Graph
Running and Analyzing the Graph
Single Kernel Development
Adding a PL Kernel Project to the System
Configuring the HW-Link Project
Adding a PS Application to the System
Building and Running the System
Building a Bare-metal AI Engine in the Vitis IDE
Programming Device and Flash Memory
Debugging the AI Engine Application
Launching Debug from the Vitis IDE
Using printf for Event Tracing
Hardware Emulation Debug from the Vitis IDE
Hardware Debug from the Vitis IDE
Bare-metal Debug from the Vitis IDE
Launching Debug from the Command Line
Hardware Emulation Debug from the Command Line
Debugging Only the AI Engine Graph
Hardware Debug from the Command line
Debugging Only the AI Engine Hardware
Using the Debug Environment
Viewing Data from Window Interfaces
Viewing Data from Stream Interfaces
Pipeline View for Single Kernel Debug
Adaptive Data Flow Graph Specification Reference
Return Code
Graph Objects
graph
kernel
port<T>
parameter
bypass
Graph Objects for Packet Processing
Platform Objects
platform<#in,#out>
FileIO
GMIO
PLIO
Event API
Connections
Connection Constructor Templates
Port Combinations
Constraints
constraint<T>
constraint< std::vector<T>>
Mapping Constraints
JSON Constraints
Node Constraints
Tile Constraint
Shim Constraint
Reserved Memory Constraint
Colocated Nodes Constraint
Not Colocated Nodes Constraint
Colocated Reserved Memories Constraint
Not Colocated Reserved Memories Constraint
Port Constraints
Buffers Constraint
Colocated Nodes Constraint
Not Colocated Nodes Constraint
Colocated Ports Constraint
Not Colocated Ports Constraint
Exclusive Colocated Ports Constraint
Colocated Reserved Memories Constraint
Not Colocated Reserved Memories Constraint
Global Constraints
AreaGroup Constraint
IsomorphicGraphGroup Constraint
Event Trace Reference
Simulation Event Trace
Using the Restrict Keyword in AI Engine Kernels
Pointer Aliasing
Strict Aliasing Rule
Restrict Keyword
Restrict Qualification
Undefined Behavior
Scope of Restrict in Inline Function
Benefits of Using Restrict for Read/Modify/Write Loops
Derived Pointers
Summary
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Please Read: Important Legal Notices

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