Vivado Design Suite User Guide: Design Flows Overview (UG892) - 2020.2 English

Document ID: UG892
Release Date: 2021-02-12
Version: 2020.2 English

Revision History
Vivado System-Level Design Flows
Industry Standards-Based Design
Design Flows
RTL-to-Bitstream Design Flow
RTL Design
IP Design and System-Level Design Integration
IP Subsystem Design
I/O and Clock Planning
Xilinx Platform Board Support
Synthesis
Design Analysis and Simulation
Placement and Routing
Hardware Debug and Validation
Alternate RTL-to-Bitstream Design Flows
Accelerated Kernel Flows
Embedded Processor Design
Model-Based Design Using Model Composer
Model-Based DSP Design Using Xilinx System Generator
High-Level Synthesis C-Based Design
Dynamic Function Exchange Design
Hierarchical Design
Understanding Use Models
Vivado Design Suite Use Models
Working with the Vivado Integrated Design Environment (IDE)
Launching the Vivado IDE on Windows
Launching the Vivado IDE from the Command Line on Windows or Linux
Launching the Vivado IDE from the Vivado Design Suite Tcl Shell
Working with Tcl
Launching the Vivado Design Suite Tcl Shell
Launching the Vivado Tools Using a Batch Tcl Script
Using the Vivado IDE with a Tcl Flow
Using Xilinx XHub Stores
Xilinx Tcl Apps
Board Files
Example Design
Understanding Project Mode and Non-Project Mode
Project Mode
Non-Project Mode
Feature Differences
Command Differences
Using Third-Party Design Software Tools
Running Logic Synthesis
Running Logic Simulation
Interfacing with PCB Designers
Using Project Mode
Project Mode Advantages
Creating Projects
Different Types of Projects
Managing Source Files in Project Mode
Using Remote, Read-Only Sources
Archiving Projects
Creating a Tcl Script to Recreate the Project
Working with a Revision Control System
Understanding the Flow Navigator
Performing System-Level Design Entry
Automated Hierarchical Source File Compilation and Management
RTL Development
RTL Elaboration and Analysis
Timing Constraint Development and Verification
Working with IP
Configuring IP
Generating IP Output Products
Using IP Core Containers
Out-of-Context Design Flow
IP Constraints
Validating the IP
Using Memory IP
Packaging Custom IP and IP Subsystems
Upgrading IP
Creating IP Subsystems with IP Integrator
Building IP Subsystems
Block Design Containers
Referencing RTL Modules in Block Designs
Designer Assistance
Using the Platform Board Flow
Validating IP Subsystems
Generating Block Design Output Products
Integrating the Block Design into a Top-Level Design
Logic Simulation
Simulation Flow Overview
Compiling Simulation Libraries
Simulation Time Resolution
Functional Simulation Early in the Design Flow
Using Structural Netlists for Simulation
Timing Simulation
Simulation Flow
Integrated Simulation
Batch Simulation
Running Logic Synthesis and Implementation
Logic Synthesis
Implementation
Configuring Synthesis and Implementation Runs
Creating and Managing Runs
Managing Runs with the Design Runs Window
Resetting Runs
Launching Runs on Remote Clusters
Performing Implementation with Incremental Compile
Implementing Engineering Change Orders (ECOs)
Viewing Log Files, Messages, Reports, and Properties
Viewing Log Files
Viewing Messages
Viewing Reports
Viewing or Editing Device Properties
Opening Designs to Perform Design Analysis and Constraints Definition
Opening an Elaborated RTL Design
Opening a Synthesized Design
Opening an Implemented Design
Updating Out-of-Date Designs
Using View Layouts to Perform Design Tasks
Saving Design Changes
Saving Changes to Original XDC Constraint Files
Saving Changes to a New Constraint Set
Closing Designs
Analyzing Implementation Results
Running Timing Analysis
Running Reports: DRC, Power, Utilization Analysis
Device Programming, Hardware Verification, and Debugging
Implementing Engineering Changes (ECOs) for Debugging
Using Project Mode Tcl Commands
Project Mode Tcl Script Examples
RTL Project Tcl Script
Netlist Project Tcl Script
Using Non-Project Mode
Non-Project Mode Advantages
Reading Design Sources
Managing Source Files
Working with a Revision Control System
Using Third-Party Synthesized Netlists
Working with IP and IP Subsystems
Running Logic Simulation
Running Logic Synthesis and Implementation
Generating Reports
Using Design Checkpoints
Performing Design Analysis Using the Vivado IDE
Opening the Vivado IDE From the Active Design
Saving Design Changes to the Active Design
Opening Design Checkpoints in the Vivado IDE
Saving Design Changes to Design Checkpoints
Using Non-Project Mode Tcl Commands
Non-Project Mode Tcl Script Example
Source Management and Revision Control Recommendations
Interfacing with Revision Control Systems
Revision Control Philosophy from 2020.2 Onwards
Revision Control Philosophy Pre 2020.2
Generating a Script to Recreate a Design
Revision Controlling Projects with Only RTL Sources
Revision Controlling Xilinx IP
Managing Custom IP Repositories
Revision Controlling Block Diagrams
Other Files to Revision Control
Output Files to Optionally Revision Control
Archiving Designs
Managing Hardware Manager Projects and Sources
When Using Vivado Design Suite Projects
Managing Vivado Lab Edition Sources
Additional Resources and Legal Notices
Xilinx Resources
Solution Centers
Documentation Navigator and Design Hubs
References
Training Resources
Please Read: Important Legal Notices

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