Vivado Design Suite User Guide: Implementation (UG904) - 2020.2 English

Document ID: UG904
Release Date: 2021-02-26
Version: 2020.2 English

Revision History
Preparing for Implementation
About the Vivado Implementation Process
SDC and XDC Constraint Support
Multithreading with the Vivado Tools
Tcl API Supports Scripting
Navigating Content by Design Process
Managing Implementation
Project Mode and Non-Project Modes
Project Mode
Working in Project Mode
Flow Navigator
Non-Project Mode
Similarities and Differences Between Project Mode and Non-Project Mode
Beginning the Implementation Flow
Importing Previously Synthesized Netlists
Starting From RTL Sources
Creating and Opening the Synthesized Design in Non-Project Mode
Loading the Design Netlist in Project Mode Before Implementation
Configuring, Implementing, and Verifying IP
Guiding Implementation with Design Constraints
Physical Constraints Definition
Timing Constraints Definition
Power Constraints Definition
UCF Format Not Supported
Constraint Sets Apply Lists of Constraint Files to Your Design
Adding Constraints as Attribute Statements
Using Checkpoints to Save and Restore Design Snapshots
Writing Checkpoint Files
Reading Checkpoint Files
Implementing the Design
Running Implementation in Non-Project Mode
Non-Project Mode Example Script
Key Steps in Non-Project Mode Example Script
Step 1: Read Design Source Files
Step 2: Build the In-Memory Design
Step 3: Read Design Constraints
Step 4: Perform Logic Optimization
Step 5: Place the Design
Step 6: Route the Design
Step 7: Run Required Reports
Step 8: Save the Design Checkpoint
Running Implementation in Project Mode
Creating Implementation Runs
Defining Implementation Runs
Using the Design Runs Window
Specifying Design Run Settings
Strategy
Description
Modifying Command Options
Save Strategy As
Verifying Run Status
Resetting Runs
Deleting Runs
Customizing Implementation Strategies
Accessing Implementation Settings for the Active Run from Flow Navigator
Defining Implementation Strategies
Accessing Currently Defined Strategies
Reviewing, Copying, and Modifying Strategies
Sharing Run Strategies
Launching Implementation Runs
Moving Processes to the Background
Running Implementation in Steps
How to Run Implementation in Steps
About Implementation Commands
Implementation Sub-Processes
Opening the Synthesized Design
Creating the In-Memory Design
Tcl Commands
synth_design
open_checkpoint
open_run
link_design
BUFG Optimization
Logic Optimization
Common Design Errors
Available Logic Optimizations
Retargeting (Default)
Constant Propagation (Default)
Sweep (Default)
Mux Optimization
Carry Optimization
Control Set Merging
Equivalent Driver Merging
BUFG Optimization (Default)
MBUFG Optimization
Shift Register Optimization (Default)
Shift Register Remap
DSP Register Opt
Control Set Reduction
Module-Based Fanout Optimization
Remap
Aggressive Remap
Resynth Area
Resynth Sequential Area
Block RAM Power Optimization (Default)
Property-Only Optimization
opt_design
Using Directives
Using the -debug_log and -verbose Options
Logic Optimization Constraints
Logic Preservation
Logic Optimization
Power Optimization
Vivado Tools Power Optimization
Using Clock Enables (CEs)
Intelligent Clock Gating
power_opt_design
Placement
Design Placement Optimization
Design Rule Checks
Clock and I/O Placement
Global Placement, Detailed Placement, and Post-Placement Optimization
Global Placement
Floorplanning Phase
Physical Synthesis Phase
Detailed Placement
Post-Placement Optimization
place_design
Using Directives
Placer Directives
Available Directives
Using the -unplace Option
Using the -no_timing_driven Option
Using the -timing_summary Option
Using the -verbose Option
Using the -post_place_opt Option
Using the no_psip Option
Using the -no_bufg_opt Option
Auto-Pipelining
Using the AXI Register Slice in Auto-Pipelining Mode
Using Auto-Pipelining on Custom Interfaces
Reviewing the Auto-Pipelining Implementation Results
Physical Optimization
Available Physical Optimizations
High-Fanout Optimization
Placement-Based Optimization
Routing Optimization
Rewiring
Critical-Cell Optimization
DSP Register Optimization
Block RAM Register Optimization
URAM Register Optimization
Shift Register Optimization
Critical Pin Optimization
Block RAM Enable Optimization
Hold-Fixing
Aggressive Hold-Fixing
Negative-Edge Register Insertion
Retiming
Forced Net Replication
SLR-Crossing Optimization
SLL Register Hold Fix
Clock Optimization
Routing Optimization
Path Group Optimization
Physical Optimization Messages
phys_opt_design
Using Directives
Using the -verbose Option
Physical Optimization Constraints
Physical Optimization Reports
Interactive Physical Optimization
Retrofitting phys_opt_design Netlist Changes
Repeating phys_opt_design Design Changes
Interactive Physical Optimization Command Reference
Routing
Design Rule Checks
Routing Priorities
Impact of Poor Timing Constraints
Router Timing Summary
route_design
Using Directives
Trading Compile Time for Better Routing
Using Other route_design Options
Routing Example Script 1
Routing Example Script 2
Routing Example Script 3
Routing Example Script 4
Router Messaging
Intermediate Route Results
Incremental Implementation
Incremental Implementation Flow Designs
Incremental Directives
Incremental Modes
Automatic Incremental
High Reuse Mode
Low Reuse Mode
Running Incremental Place and Route
read_checkpoint -incremental
Incremental Implementation Controls
Using report_incremental_reuse
Factors Affecting Run Time Improvement
Using Incremental Implementation
Using Incremental Implementation in Non-Project Mode
Using Incremental Implementation in Project Mode
Orphaned Route Segments
Using Synplify Compile Points
Using Incremental Synthesis
Saving Post-Reuse Checkpoints
Constraint Conflicts
Incremental Compile Advanced Analysis
Reuse Reporting
Incremental Reuse Summary
Hierarchical Implementation Reuse Summary
Hierarchical Implementation Reuse Summary
Timing Reports
Object Properties
Analyzing and Viewing Implementation
Monitoring the Implementation Run
Viewing the Run Status Display
Canceling or Resetting the Run
Viewing the Log in the Log Window
Pausing Output
Displaying the Project Status
Viewing Project Status in the Project Status Bar
Viewing Out-of-Date Status
Forcing Runs Up-to-Date
Moving Forward After Implementation
Recommended Steps After Implementation
Moving Forward in Non-Project Mode
Moving Forward in Project Mode
Viewing Messages
Viewing Messages in Non-Project Mode
Viewing Messages in Project Mode
Incremental Compile Messages
Viewing Implementation Reports
Reporting in Non-Project Mode
Opening Reports in a Vivado IDE Window
Getting Help with Implementation Reports
Reporting in Project Mode
Cross Probing from Reports
Cross Probing Between Timing Report and Device Window Example
Modifying Implementation Results
Modifying Placement
Fixing Placer-Placed Logic
Placing and Moving Logic by Hand
Placing Logic using a Tcl Command
Modifying Routing
Manual Routing
Manual Routing Rules
Entering Assign Routing Mode
Routing Assignment Window
Assigning Routing Nodes
Un-Assigning Routing Nodes
Exiting Assign Routing Mode
Canceling Out of Assign Routing Mode
Verifying Assigned Routes
Branching
Assigning Routing to a Branch
Locking Cell Inputs and Adding DONT_TOUCH Constraint on LUT Loads
Directed Routing Constraints
Using the find_routing_path Command to Create Directed Routing
Modifying Logic
Saving Modifications
Modifying the Netlist
Netlist Modifying Commands
Use Cases
Use Case 1: Inverting the Logical Value of a Net
Use Case 2: Adding a Debug Port
Use Case 3: Adding a Pipeline Stage to Improve Timing
Vivado ECO Flow
ECO Flow Chart
ECO Navigator Use
Edit Section
Run Section
Report Section
Program Section
Scratch Pad
Scratch Pad Toolbar Commands
Scratch Pad Pop-up Menu
Schematic Window
Using Remote Hosts and Compute Clusters
Overview
Requirements
Manual Configuration
Setting Up SSH Key Agent Forward
Cluster Configurations
SLURM Specific Configuration
Launching Jobs on Remote Hosts
ISE Command Map
Tcl Commands and Options
Implementation Categories, Strategy Descriptions, and Directive Mapping
Implementation Categories
Implementation Strategy Descriptions
Directives Used by opt_design and place_design in Implementation Strategies
Directives Used by phys_opt_design and route_design in Implementation Strategies
Listing the Strategies for a Release
Listing the Directives for a Release
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Training Resources
Please Read: Important Legal Notices

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