Vivado Design Suite Tutorial: Model-Based DSP Design Using System Generator (UG948) - 2020.2 English

Document ID: UG948
Release Date: 2020-12-11
Version: 2020.2 English

Revision History
System Generator for DSP Overview
Software Requirements
Configuring MATLAB to the Vivado Design Suite
Locating and Preparing the Tutorial Design Files
Introduction to System Generator
Step 1: Creating a Design in an FPGA
Configure the System Generator Blocks
Review the Results
Step 2: Creating an Optimized Design in an FPGA
Step 3: Creating a Design Using Discrete Components
Step 4: Working with Data Types
Part 1: Designing with Floating-Point Data Types
Part 2: Designing with Fixed-Point Data Types
Summary
Importing Code into System Generator
Step 1: Modeling Control with M-Code
Step 2: Modeling Blocks with HDL
Step 3: Modeling Blocks with C/C++ Code
Part 1: Creating a System Generator Package from Vitis HLS
Part 2: Including a Vitis HLS Package in a System Generator Design
Summary
Timing and Resource Analysis
Step 1: Timing Analysis in System Generator
Troubleshooting the Timing Violations
Step 2: Resource Analysis in System Generator
Summary
Working with Multi-Rate Systems
Step 1: Creating Clock Domain Hierarchies
Step 2: Creating Asynchronous Channels
Step 3: Specifying Clock Domains
Summary
Using AXI Interfaces and IP Integrator
Step 1: Review the AXI Interfaces
Step 2: Create a Vivado Project using System Generator IP
Step 3: Create a Design in IP Integrator
Step 4: Implement the Design
Summary
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
Please Read: Important Legal Notices

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