quad_spi_if Project Status (08/20/2010 - 01:16:58) | |||
Project File: | quad_spi_if.xise | Parser Errors: | X 2 Errors |
Module Name: | quad_spi_if | Implementation State: | Synthesized |
Target Device: | xc6slx45-2csg324 |
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No Errors |
Product Version: | ISE 12.2 |
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239 Warnings (0 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice Registers | 385 | 54576 | 0% | |
Number of Slice LUTs | 443 | 27288 | 1% | |
Number of fully used LUT-FF pairs | 278 | 550 | 50% | |
Number of bonded IOBs | 255 | 218 | 116% | |
Number of BUFG/BUFGCTRLs | 1 | 16 | 6% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Thu Sep 9 13:11:36 2010 | 0 | 239 Warnings (0 new) | 10 Infos (0 new) | |
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |