quad_spi_if Project Status (08/20/2010 - 01:16:58)
Project File: quad_spi_if.xise Parser Errors: X 2 Errors
Module Name: quad_spi_if Implementation State: Synthesized
Target Device: xc6slx45-2csg324
  • Errors:
No Errors
Product Version:ISE 12.2
  • Warnings:
239 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 385 54576 0%
Number of Slice LUTs 443 27288 1%
Number of fully used LUT-FF pairs 278 550 50%
Number of bonded IOBs 255 218 116%
Number of BUFG/BUFGCTRLs 1 16 6%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu Sep 9 13:11:36 20100239 Warnings (0 new)10 Infos (0 new)
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 09/09/2010 - 17:24:33