
################################################################
# This is a generated script based on design: Z
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################

################################################################
# Check if script is running in correct Vivado version.
################################################################
#set scripts_vivado_version 2014.2
#set current_vivado_version [version -short]
#
#if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
#   puts ""
#   puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."
#
#   return 1
#}

################################################################
# START
################################################################

# To test this script, run the following commands from Vivado Tcl console:
# source Z_script.tcl

# If you do not already have a project created,
# you can create a project using the following command:
#    create_project project_1 myproj -part xc7z045ffg900-2
#    set_property BOARD_PART xilinx.com:zc706:part0:1.0 [current_project]


# CHANGE DESIGN NAME HERE
set design_name remusbup

# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
#    create_bd_design $design_name

# CHECKING IF PROJECT EXISTS
if { [get_projects -quiet] eq "" } {
   puts "ERROR: Please open or create a project!"
   return 1
}


# Creating design if needed
set errMsg ""
set nRet 0

set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]

if { ${design_name} ne "" && ${cur_design} eq ${design_name} } {

   # Checks if design is empty or not
   if { $list_cells ne "" } {
      set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
      set nRet 1
   } else {
      puts "INFO: Constructing design in IPI design <$design_name>..."
   }
} elseif { ${cur_design} ne "" && ${cur_design} ne ${design_name} } {

   if { $list_cells eq "" } {
      puts "INFO: You have an empty design <${cur_design}>. Will go ahead and create design..."
   } else {
      set errMsg "ERROR: Design <${cur_design}> is not empty! Please do not source this script on non-empty designs."
      set nRet 1
   }
} else {

   if { [get_files -quiet ${design_name}.bd] eq "" } {
      puts "INFO: Currently there is no design <$design_name> in project, so creating one..."

      create_bd_design $design_name

      puts "INFO: Making design <$design_name> as current_bd_design."
      current_bd_design $design_name

   } else {
      set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
      set nRet 3
   }

}

puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"."

if { $nRet != 0 } {
   puts $errMsg
   return $nRet
}

##################################################################
# DESIGN PROCs
##################################################################


# Hierarchical cell: DP_CHKR
proc create_hier_cell_DP_CHKR { parentCell nameHier } {

  if { $parentCell eq "" || $nameHier eq "" } {
     puts "ERROR: create_hier_cell_DP_CHKR() - Empty argument(s)!"
     return
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     puts "ERROR: Unable to find parent cell <$parentCell>!"
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj

  # Create cell and set as current instance
  set hier_obj [create_bd_cell -type hier $nameHier]
  current_bd_instance $hier_obj

  # Create interface pins
  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI
  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI3

  # Create pins
  create_bd_pin -dir I -type clk LA_Clk
  create_bd_pin -dir I -type rst axi_aresetn
  create_bd_pin -dir O bpg_de
  create_bd_pin -dir O bpg_hs
  create_bd_pin -dir O -from 35 -to 0 bpg_out
  create_bd_pin -dir O bpg_vs
  create_bd_pin -dir I -type clk clk
  create_bd_pin -dir I -from 127 -to 0 debug_ina1_127_0
  create_bd_pin -dir I -from 127 -to 0 debug_inb1_127_0
  create_bd_pin -dir I -from 127 -to 0 debug_inb3_127_0
  create_bd_pin -dir I -from 15 -to 0 debug_inb3_ext_15_0
  create_bd_pin -dir I dp_live_video_out_de
  create_bd_pin -dir I dp_live_video_out_hsync
  create_bd_pin -dir I -from 35 -to 0 dp_live_video_out_pixel1
  create_bd_pin -dir I dp_live_video_out_vsync
  create_bd_pin -dir I -from 31 -to 0 gpio_in
  create_bd_pin -dir O -from 31 -to 0 gpio_systype

  # Create instance: axi_dpchk_1, and set properties
  set axi_dpchk_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dpchk:4.00.a axi_dpchk_1 ]

  # Create instance: axi_monitor_0, and set properties
  set axi_monitor_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_monitor:1.00.c axi_monitor_0 ]
  set_property -dict [ list CONFIG.C_DEPTH_MUL {8} CONFIG.C_SYSTEM_TYPE {0x80800000} CONFIG.C_S_AXI_ID_WIDTH {6}  ] $axi_monitor_0

  # Create interface connections
  connect_bd_intf_net -intf_net axi_interconnect_3_M05_AXI [get_bd_intf_pins S_AXI] [get_bd_intf_pins axi_dpchk_1/S_AXI]
  connect_bd_intf_net -intf_net axi_interconnect_3_M06_AXI [get_bd_intf_pins S_AXI3] [get_bd_intf_pins axi_monitor_0/S_AXI3]

  # Create port connections
  connect_bd_net -net axi_dpchk_1_bpg_de [get_bd_pins bpg_de] [get_bd_pins axi_dpchk_1/bpg_de]
  connect_bd_net -net axi_dpchk_1_bpg_hs [get_bd_pins bpg_hs] [get_bd_pins axi_dpchk_1/bpg_hs]
  connect_bd_net -net axi_dpchk_1_bpg_out [get_bd_pins bpg_out] [get_bd_pins axi_dpchk_1/bpg_out]
  connect_bd_net -net axi_dpchk_1_bpg_vs [get_bd_pins bpg_vs] [get_bd_pins axi_dpchk_1/bpg_vs]
  connect_bd_net -net axi_dpchk_1_dbg0_ext_o [get_bd_pins axi_dpchk_1/dbg0_ext_o] [get_bd_pins axi_monitor_0/debug_inc0_ext_15_0]
  connect_bd_net -net axi_dpchk_1_dbg0_o [get_bd_pins axi_dpchk_1/dbg0_o] [get_bd_pins axi_monitor_0/debug_inc0_127_0]
  connect_bd_net -net axi_dpchk_1_dbg1_ext_o [get_bd_pins axi_dpchk_1/dbg1_ext_o] [get_bd_pins axi_monitor_0/debug_ind0_ext_15_0]
  connect_bd_net -net axi_dpchk_1_dbg1_o [get_bd_pins axi_dpchk_1/dbg1_o] [get_bd_pins axi_monitor_0/debug_ind0_127_0]
  connect_bd_net -net axi_dpchk_1_err_out8_o [get_bd_pins axi_dpchk_1/err_out8_o] [get_bd_pins axi_monitor_0/err_in8]
  connect_bd_net -net axi_monitor_0_gpio_systype [get_bd_pins gpio_systype] [get_bd_pins axi_monitor_0/gpio_systype]
  connect_bd_net -net axi_monstub_0_debug_out_b_127_0 [get_bd_pins debug_ina1_127_0] [get_bd_pins axi_monitor_0/debug_ina1_127_0]
  connect_bd_net -net axi_monstub_1_debug_out_a_127_0 [get_bd_pins debug_inb3_127_0] [get_bd_pins axi_monitor_0/debug_inb3_127_0]
  connect_bd_net -net axi_monstub_1_debug_out_a_ext_15_0 [get_bd_pins debug_inb3_ext_15_0] [get_bd_pins axi_monitor_0/debug_inb3_ext_15_0]
  connect_bd_net -net clk_wiz_0_clk_out1 [get_bd_pins clk] [get_bd_pins axi_dpchk_1/clk] [get_bd_pins axi_dpchk_1/vid_clk_i] [get_bd_pins axi_monitor_0/Clk]
  connect_bd_net -net dp_1_dp_live_video_de_out [get_bd_pins dp_live_video_out_de] [get_bd_pins axi_dpchk_1/dp_live_video_out_de]
  connect_bd_net -net dp_1_dp_live_video_hsync_out [get_bd_pins dp_live_video_out_hsync] [get_bd_pins axi_dpchk_1/dp_live_video_out_hsync]
  connect_bd_net -net dp_1_dp_live_video_pixel1_out [get_bd_pins dp_live_video_out_pixel1] [get_bd_pins axi_dpchk_1/dp_live_video_out_pixel1]
  connect_bd_net -net dp_1_dp_live_video_vsync_out [get_bd_pins dp_live_video_out_vsync] [get_bd_pins axi_dpchk_1/dp_live_video_out_vsync]
  connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_pins LA_Clk] [get_bd_pins axi_monitor_0/LA_Clk]
  connect_bd_net -net rst_clk_wiz_0_25M_peripheral_aresetn [get_bd_pins axi_aresetn] [get_bd_pins axi_dpchk_1/axi_aresetn] [get_bd_pins axi_monitor_0/Rst_n]
  connect_bd_net -net xlconcat_2_dout [get_bd_pins debug_inb1_127_0] [get_bd_pins axi_monitor_0/debug_inb1_127_0]
  connect_bd_net -net xlconstant_4_const [get_bd_pins gpio_in] [get_bd_pins axi_monitor_0/gpio_in]
  
  # Restore current instance
  current_bd_instance $oldCurInst
}


# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {

  if { $parentCell eq "" } {
     set parentCell [get_bd_cells /]
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     puts "ERROR: Unable to find parent cell <$parentCell>!"
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj


  # Create interface ports

  # Create ports

  # Create instance: DP_CHKR
  create_hier_cell_DP_CHKR [current_bd_instance .] DP_CHKR

  # Create port connections

  # Create address segments
  

  # Restore current instance
  current_bd_instance $oldCurInst

  save_bd_design
}
# End of create_root_design()


##################################################################
# MAIN FLOW
##################################################################

create_root_design ""


