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 /___/  \  /
 \   \   \/    ? Copyright 2015 Xilinx, Inc. All rights reserved.
  \   \        This file contains confidential and proprietary
  /   /        information of Xilinx, Inc. and is protected under U.S.
 /___/   /\    and international copyright and other intellectual
 \   \  /  \   property laws.
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Vendor: Xilinx
Current README.txt Version: 1.0.0
Date Created              : 31JULY2015

Associated Filename: xapp1266-qos-zc702-2015-2.zip
Associated Document: http://www.wiki.xilinx.com/Zynq+Base+TRD+2015.2
		     US873 - Zynq Concepts, Tools and Techniques
		     UG798 - Xilinx Design Tools: Installation and Licensing Guide
		     UG925 - Zynq-7000 ZC702 Evaluation Kit User Guide
		     UG850 - ZC702 Evaluation Board User Guide
Supported Device(s): XC7Z020-1CLG484

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      This disclaimer is not a license and does not grant any rights to
      the materials distributed herewith. Except as otherwise provided in
      a valid license issued to you by Xilinx, and to the maximum extent
      permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE
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THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS
FILE AT ALL TIMES.

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The video_qt application shipped with this reference design is based in
part on the work of the Qwt project (http://qwt.sf.net).

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The applications shipped with this reference design include Linux kernel
header files and are not considered a "derivative work" for the purposes
of the GPL.

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This readme file contains these sections:

1. REVISION HISTORY
2. OVERVIEW
3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS
4. DESIGN FILE HIERARCHY
5. INSTALLATION AND OPERATING INSTRUCTIONS
6. OTHER INFORMATION
7. SUPPORT

1. REVISION HISTORY


            Readme
Date        Version      Revision Description
=========================================================================
31JUL2015   1.0.0  Zynq Base TRD 2015.2
			    ~ IPs and Software upgraded for 2015.2 tool version.
			    ~ Use AXI IIC instead of PS I2C1(EMIO).
			    ~ Petalinux 2015.2
			    ~ Xilinx APM driver.
			    ~ LogicCVC Display driver.
=========================================================================

2. OVERVIEW

This application note describes the use case where QoS block can be configured 
for system applications that does not guaranteed the bandwidth, but limits the 
bandwidth of other master in advance QoS and also the usage of AXI HP QoS signals 
in Basic QoS. In Zynq-7000 All Programmable SoC, it is possible to implement 
basic QoS and Advanced QoS options depending on the system requirement. 
The application uses the AXI Traffic generator (ATG) IP to generate the traffic 
on one of the Zynq-7000 Processing System???s AXI High Performance Port, AXI 
Coherency Port (ACP) and the Test pattern Generator (TPG) on one AXI HP Port 
and Sobel filter on another AXI HP Port. ATG generates traffic congestion 
scenario by writing into DDR using AXI HP Port. The Linux application running 
on Zynq device that controls the congestion by enabling the QoS block for the 
CPU, QoS signals of AXI HP Ports and DDR ports. The performance of the ATG, 
TPG and Sobel filter  are measured using AXI Performance Monitor IP.

The package consists of two video based application projects which differ
in user interface.
a) video_qt application has a graphical user interface designed
using QT framework.
b) QoS configuration scripts used for different modes of QoS.

For information on how to use this package, along with build instructions,
please refer http://www.wiki.xilinx.com/Zynq+Base+TRD+2015.2

3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS

Software:
  -- Vivado Design Suite 2015.2
  -- Proper installation of required license files for the TRD.
  -- Optional: ZC702 board uses CP210x USB to UART Bridge to provide COM port
     connection to the board. This configuration is highly recommended because
     the UART outputs information to hyper terminal right after power up.
     To use this feature, hyper terminal, Minicom, teraterm or equivalent
     terminal software on the host machine is required. For details, please
     refer to UG925 for USB-to-UART Bridge driver installation.
  -- For additional information on software installation, refer to UG798.

Hardware:
  -- The reference design targets the Zynq ZC702 evaluation board, Rev C or
     above.
  -- ZC702 evaluation board setup in the default configuration as documented
     in the Default Switch and Jumper Setting of UG850.
  -- AC power adapter (12VDC)
  -- HDMI-to-HDMI or HDMI-to-DVI cable (depending on available Monitor)
  -- Monitor capable of supporting 1080p60 / 720p60
  -- USB Type-A Female to USB Micro-B Male cable
  -- USB hub
  -- USB mouse
  -- Optional: USB Type A Male to USB Mini-B Male cable if using USB-to-UART
     bridge
  -- SD memory card reader for transferring files onto the SD card.
     (not included in the package)


4. DESIGN FILE HIERARCHY


The directory structure underneath this top-level folder is described
below:

\Source
 |
 +----- \doc
 |
 |           +--\lgpl-2.1.txt
 |                 Copy of LGPL LICENSE
 |
 |           +--\README.txt
 |              This file
 |
 +----- \hardware
 |           +--\vivado
 |              Vivado hardware project for TRD design
 |
 |           +--\vivado_hls
 |              Vivado HLS project .The C-algorithm for the sobel
 |              filter that gets synthesized to an RTL pcore
 |
 +----- \ready_to_test
 |
 |           +--\BOOT.BIN
 |              Zynq Boot Image, which is created from
 |              FSBL, hardware bitstream and u-boot
 |
 |           +--\uImage
 |              Xilinx Linux kernel
 |
 |           +-- devicetree.dtb
 |	        Device tree with TPG support.
 |
 |
 |           +--\uramdisk.image.gz
 |	        ramdisk image with third party libs/apps(DRM,V4Ls)
 |
 |           +--\autostart.sh
 |              TRD init script.
 |
 |           +--\bin\atg_on.sh
 |              ATG start and stop script for basic QoS.
 |
 |           +--\bin\qos_on.sh
 |              Basic QoS configuration script.
 |
 |           +--\bin\atg_acp.sh
 |              ATG start and stop script for advance QoS.
 |
 |           +--\bin\aqos_en.sh
 |              Advance QoS configuration script.
 |
 |           +--\bin
 |				Contains video cmd and QT applications.
 +----- \software
 |
 |           +--\petalinux
 |              Petalinux project.
 |              Includes-
 |              Kernel,u-boot configurations.
 |              User application and libraries.
 |              Dynamic libraries and helper utilities of DRM/KMS/multimedia/V4L2 framework
 |
 |          +--\xsdk
 |             TRD application/libraries for XSDK.
 |             Headers of DRM/KMS/multimedia framework.
 |             Xilinx Linux 3.19 kernel exported headers.
 |             Dynamic libraries for DRM/V4L2/multimedia/V4L2/OpenCV.

5. INSTALLATION AND OPERATING INSTRUCTIONS


ZC702 Initial Setup:
--------------------

-- All jumpers and switches should be in default setting except SW16.
   Mode switch SW16 should be set to boot from SD card.
   See image for SD boot in User Guide (UG925).
   For a board with SW16, use the following configuration
   1: GND
   2: GND
   3: VCC
   4: VCC
   5: GND
   J21, J20, J22, J25, J26: Unstuffed
   For Rev C version of the board which does not have SW16,
   use the following jumper settings:
   J21: 2-3
   J20: 2-3
   J22: 1-2
   J25: 1-2
   J26: 2-3
-- Connect one end of the HDMI cable to board HDMI connector, connect the other
   end to the monitor's HDMI or DVI input
-- Connect USB Micro-B cable to on-board USB Micro connector J1, then connect up
   USB hub, mouse and keyboard.
-- connect the AC power adapter
-- Optional: If USB-to-UART bridge is used, connect USB Mini-B side of USB-to-
   Mini-B cable to the on-board mini USB connector (J17). Connect USB side to
   the control PC.

Building Design:
----------------

Instructions to Build Hardware and Software for this TRD are available at
http://www.wiki.xilinx.com/Zynq+Base+TRD+2015.2

The pre compiled files are kept in ready_to_test directory and can be loaded on SD card
root to get started with the design. On Linux boot up the TRD application is
auto loaded and GUI comes on the screen. Here various options can be explored.

For more details on how to Run the TRD please see User Guide.

6.OTHER INFORMATION

1) Design Notes
	Not applicable.

2) Known Issues
	(1) In TPG selection, when the bouncing box touches the boundary of the
            monitor there is a horizontal line appears on the monitor.
	(2) In QoS selection, we are switch off and on the video pipeline during
			basic and advance QoS configuration.
7. SUPPORT

To obtain technical support for this reference design, go to www.xilinx.com/support
to locate answers to known issues in the Xilinx Answers Database.
