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logiCVC-ML revision log

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VERSION  |  DATE         |  DESCRIPTION
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1.06.c   |  21.04.2010.  |  Initial LVIP release edition
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2.00.a   |  16.09.2010.  |  New features:
         |               |     - Added AXI4 master interface
         |               |     - Added AXI4-Lite slave interface
         |               |     - Added C_REGS_LITTLE_ENDIAN generic
         |               |       parameter
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2.01.a   |  14.03.2011.  |  New features:
         |               |     - Added DVI output interface
         |               |     - Removed camera link 3-bit interface
         |               |     - Parallel interface always available
         |               |     - Added support for Xilinx Kintex7
         |               |       FPGA family
         |               |  Bug fix:
         |               |     - Blank signal now synchronous to data
         |               |       on 12-bit parallel output interface
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2.04.a   |  08.02.2012.  |  New features:
         |               |     - Added XCOLOR dithering module
         |               |     - Added support for Xilinx 7-seriers
         |               |       FPGA families (Artix7, Kintex7,
         |               |       Virtex7)
         |               |     - Removed serialized blender
         |               |     - New version generic parameters added:
         |               |       C_IP_LICENSE_CHECK, C_IP_TIME_BEFORE_BREAK
         |               |     - IP_VERSION register updated accordingly
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2.05.a   |  21.03.2012.  |  New features:
         |               |     - Added support for YCbCr 4:4:4 and YCbCr 4:2:2
         |               |       display output
         |               |     - Removed C_LITTLE_ENDIAN generic parameter
         |               |     - Removed C_REGS_LITTLE_ENDIAN generic parameter
         |               |     - Added C_MEM_LITTLE_ENDIAN generic parameter
         |               |     - Added C_MEM_BYTE_SWAP and C_REG_BYTE_SWAP
         |               |       generic parameters
         |               |     - Added C_USE_VCLK2 generic parameter added
         |               |     - Powre control register(PWRCTRL) readable when
         |               |       generic parameter C_READABLE_REGS = 0
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2.05.b   |  16.04.2012.  |  New features:
         |               |     - Generic parameter C_IP_TIME_BEFORE_BREAK modified
         |               |       to support release edition (0 = infinite, 1 = 1h,
         |               |       2 = 12h)
         |               |  Bug fix:
         |               |     - YCbCr 4:2:2 output generator modified
         |               |       to support average CbCr value for neighboring
         |               |       pixels
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2.05.c   |  03.05.2012.  |  Bug fix:
         |               |     - YCbCr 4:2:2 output generator bugfix
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3.00.a   |  17.09.2012.  |  New features:
         |               |     - Added C_DISPLAY_COLOR_SPACE generic that determines
         |               |       the output interface color space.
         |               |     - Added support for YCbCr 444 and 422 layers
         |               |       (C_LAYER_0_TYPE).
         |               |     - Added support for two alpha layers (alpha plane)
         |               |       so now layers 1 and 3 can be configured as alpha
         |               |       layers (C_LAYER_0_TYPE).
         |               |     - Added support for different byte ordering inside
         |               |       pixels (RGB, BGR, YCbCr, CrCbY, ...).
         |               |     - Added global rst input
         |               |     - Added C_INCREASE_FIFO generic that allows FIFO to be
         |               |       increased in size up to 8 times.
         |               |     - ITU656 444 to 422 conversion now uses average
         |               |       value of neighboring pixels.
         |               |     - ITU656 output now supports active edge setup in the
         |               |       same way as parallel output (control register).
         |               |     - Increased maximal layer vertical offset from 2048
         |               |       to 4096.
         |               |     - Removed functionality of enabling/disabling pixclk
         |               |       during hsync (ctrl reg(9)).
         |               |     - External "RGB input" name changed to "parallel input"
         |               |       as it can now also be in YCbCr format.
         |               |     - Added university evaluation version (watermark).
         |               |  Bug fix:
         |               |     - Better reset behavior when reseting the FPGA system
         |               |     - Fixed synchronization delay when external parallel
         |               |       input is used.
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3.01.a   |  07.03.2013.  |  New features:
         |               |     - Separate clocks added for different memory
         |               |       interfaces: mplb_clk for MPLB, mclk for XMB and
         |               |       m_axi_aclk for AXI4. Clock port mclk is no longer
         |               |       used as universal clock for all memory interfaces,
         |               |       but only for XMB.
         |               |     - Default value for generic parameter C_REGS_INTERFACE
         |               |       set to AXI4-Lite.
         |               |     - Default value for generic parameter C_VMEM_INTERFACE
         |               |       set to AXI4.
         |               |     - Added DVI support for 7 Series.
         |               |  Bug fix:
         |               |     - One process in v3.00.a was not beeing sythesised
         |               |       properly when targeting S3e family so it has been
         |               |       redesigned.
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3.02.a   |  03.05.2013.  |  New features:
         |               |     - Hsync and vsync are now edge aligned.
         |               |     - Added clock definition parameters on missing clock
         |               |       signals in mpd
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3.02.b   |  23.01.2014.  |  Bug fix:
         |               |     - Renamed oserdes component to dvi_oserdes to avoid
         |               |       PlanAhead error
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4.00.a   |  01.02.2014.  |  New features:
         |               |     - Added support for programmable layer address
         |               |     - Removed LAYER_OFFSET generics
         |               |     - Removed C_VMEM_BASEADDR and C_VMEM_HIGHADDR generics
         |               |     - Added LAYER_ADDR generics
         |               |     - Replaced layer offset registers with layer address
         |               |     - Removed old CPU controlled vbuff select
         |               |     - Changed layer register update trigger from vertical
         |               |       position write to layer address write
         |               |     - Added disable register update bit to control register
         |               |     - Added FIFO underrun bit to interrupt status register
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4.01.a   |  15.05.2014.  |  New features:
         |               |     - Added current CVC reading buffer output port
         |               |     - Added C_INTERCONNECT_M_AXI_READ_ISSUING parameter to
         |               |       .mpd file
         |               |     - Renamed v_en output port to en_v
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4.01.b   |  24.07.2014.  |  Bug fix:
         |               |     - Solved problem with toggling of the beggining of first
         |               |       line when implementing in Vivado.
         |               |     - Fixed overlapping request issue on AXI4-Lite slave
         |               |       interface.
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4.1.2    |  02.10.2014.  |  New features:
         |               |     - IP core version naming convention modified for Vivado
         |               |       IP-XACT package compliance. Patch level designation
         |               |       is replaced by IP core's revision tag.
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4.2.1    |  14.11.2014.  |  New features:
         |               |     - Added embedded timing signals within the video stream.
         |               |     - Added C_USE_EMB_SYNC parameter that enables/disables                          			          
         |               |       embeded syncs when the parallel display interface is 
         |               |       selected.
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