#*******************************************************************************
#Vendor: Xilinx #Associated Filename: run.tcl
#Purpose: Vivado HLS tcl script 
#                                                
#*******************************************************************************
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#*******************************************************************************

catch {eval exec "uname -m"} machine_name
catch {eval exec "uname -s"} kernel_name
catch {eval exec "vivado_hls -r"} vivado_hls_home

if {$machine_name == "x86_64" && $kernel_name == "Linux"} {
    set gcc_lib $vivado_hls_home/lnx64/tools/gcc/lib64
} elseif {$machine_name == "i686" && $kernel_name == "Linux"} {
    set gcc_lib $vivado_hls_home/lnx32/tools/gcc/lib
} else {
    set gcc_lib $vivado_hls_home/msys/lib/gcc/mingw32/4.6.2
}
set ::env(LD_LIBRARY_PATH) $gcc_lib:$::env(LD_LIBRARY_PATH)

# Create the design project
open_project prj -reset

# Define the top level function for hardware synthesis
set_top image_filter

# Select the files for hardware synthesis
add_files top.cpp
if { [info exists files] } {
    add_files $files
}

# Select the files required for the testbench
add_files -tb test.cpp
add_files -tb opencv_${module_name}.cpp
add_files -tb hls_${module_name}.cpp
add_files -tb ../common/images/test_1080p.bmp
if { [info exists tb_files] } {
    add_files -tb $tb_files
}

# Set the name of the solution for this design
open_solution "solution1"

# Select the FPGA 
set_part "xc7z020clg484-1"
create_clock -period "150MHz"

if { [info exists special_config] } {
    eval $special_config
}
config_schedule -verbose
config_core DSP48 -latency 1
# Set flags
set csim_flag 1
if { [info exists ::env(csim_flag)] } {
    set csim_flag $::env(csim_flag)
}
set csynth_flag 1
if { [info exists ::env(csynth_flag)] } {
    set csynth_flag $::env(csynth_flag)
}
set cosim_flag 0
if { [info exists ::env(cosim_flag)] } {
    set cosim_flag $::env(cosim_flag)
}
set export_flag 1
if { [info exists ::env(export_flag)] } {
    set export_flag $::env(export_flag)
}


if { $csim_flag == 1 } {
    # Vivado HLS commands for C simulation
    csim_design -mflags -j4 -O
}

if { $csynth_flag == 1 } {
    # Vivado HLS commands for C to RTL synthesis
    csynth_design
}

if { $cosim_flag == 1 } {
    # Vivado HLS commands for RTL simulation
    cosim_design
}

if { $export_flag == 1 } {
    # Vivado HLS commands for RTL implementation
    export_design
}

exit
