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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

Library UNISIM;
use UNISIM.vcomponents.all;


entity clock_mux is
  port (
    -- clock input 1
    clk_in_1 : in  std_logic;     
    -- clock input 2 
    clk_in_2 : in  std_logic;
    -- clock output
    clk_out  : out std_logic;
    -- select signal
    sel      : in  std_logic
  );
end entity clock_mux;

------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------

architecture RTL of clock_mux is
begin          
  BUFGMUX_INST : BUFGMUX
  generic map (
    CLK_SEL_TYPE => "SYNC"
  )
  port map (
    O  => clk_out,
    I0 => clk_in_1,
    I1 => clk_in_2,
    S  => sel
  );
end RTL;
