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Vendor: AMD 
Current readme.txt Version: 3.0
Date Last Modified:  19OCT2022
Date Created: 07JUN2020

Associated Filenames: qdma_v5_0_bridge_registers 
                      qdma_v5_0_pf_registers 
                      qdma_v5_0_vf_registers
Associated Documents: PG302, QDMA Subsystem for PCI Express Product Guide
                      PG344, Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide
Supported Device(s): UltraScale+, Versal Adaptive SoC
   
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This readme file contains these sections:

1. REVISION HISTORY
2. OVERVIEW
3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS
4. DESIGN FILE HIERARCHY
5. INSTALLATION AND OPERATING INSTRUCTIONS
6. OTHER INFORMATION (OPTIONAL)
7. SUPPORT


1. REVISION HISTORY 


            Readme  
Date        Version    Revision Description
=========================================================================
19OCT2022   3.0       Register .CSV file is updated for the IP core.

22APR2021   2.2       Zip file renamed. 

14APR2021   2.1       Updated associated documents and devices in readme only. Files remain the same.

24JUN2020   2.0       Added VF registers CSV, and added PF registers to CSR file and renamed CSV registers file to PF.

07JUN2020   1.0       Initial Xilinx release.
=========================================================================

2. OVERVIEW

This readme describes how to use the files that come with PG302.

Extract the contents of the ZIP, and open the comma separated value (CSV) files for register space details. 

The CSV files provide reference information as a companion to PG302. Refer to PG302 for when to use the register maps for information. 

3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS

* Xilinx Vivado 2020.2 or higher

4. SUPPORT

To obtain technical support for this reference design, go to 
www.xilinx.com/support to locate answers to known issues in the Xilinx
Answers Database.  