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Vendor: AMD
Current readme.txt Version: 3.0
Date Last Modified:  14MAY2025
Date Created: 06JUL2020

Associated Document: PG347, Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide
Associated Filenames: 
   CPM4 register files:
       cpm4-qdma-v2-1-registers.csv
       cpm4-bridge-v2-1-registers.csv
       cpm4-xdma-v2-1-registers.csv
   CPM5 register files:
       cpm5-qdma-v4-0-pf-registers.csv
       cpm5-qdma-v4-0-vf-registers.csv
       cpm5-qdma-v4-0-bridge-registers.csv
       cpm5_qdma_fab_thr_src.csv  
Supported Device(s): Versal Adaptive SoC
   
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This readme file contains these sections:

1. REVISION HISTORY
2. OVERVIEW
3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS
4. SUPPORT


1. REVISION HISTORY 

<Describe changes to the reference design ZIP file using this format>

            Readme  
Date        Version      Revision Description
=========================================================================
06JUL2020   1.0          Initial Xilinx release.
16NOV2020   2.1          Initial Public Xilinx release.
10OCT2021   3.0          Updated for CPM configuration in CIPS IP 3.0.
                         Added CPM5 registers.
                         Renamed register files.
14MAY2025   3.0          Updated global error status bit [17] 
=========================================================================

2. OVERVIEW

This readme describes how to use the files that come with PG347.

Extract the contents of the ZIP, and open the comma separated value (CSV) files for register map details. 

The CSV files provide reference information as a companion to PG347. Refer to PG347 for when to use the register maps for information. 

3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS

* AMD Vivado 2021.1 or higher

4. SUPPORT

To obtain technical support for this reference design, go to 
support.xilinx.com to locate answers to known issues in the 
Answer Records Database.  