Knowledge of using DSP simulation software and/or hardware implementations
Awareness of digital communications and modern high speed DSP applications and issues
After completing this workshop, you will be able to:
Understand the fundamentals of fixed point word lengths and related issues
Know how to control and deal with rounding, truncation, wrap-around, and saturation arithmetic on FPGAs
Understand the many arithmetic implementation options (for multiply and other operations)
Know how to design and work with Coordinate Rotation Digital Computer (CORDIC) designs for trigonometric calculations
Know the features and architectures of the DSP48x slices of the Virtex® and Spartan® FPGAs
Know how to use the Xilinx System Generator Simulink® software for DSP design
Be able to run the full ISE® software design flow for DSP systems and examples
Implement real time DSP examples on the FPGA board using audio input/output codecs
Understand the reasons for and methods to implement high-speed Cascaded Integrator-Comb (CIC) filters
Know the methods for implementation of Numerically Controlled Oscillators (NCOs)
Be able to build a QAM transceiver using various core FPGA components
Understand how to set up Phase-Locked Loops (PLLs) and early late gates for synchronization
Understand the use of the QR algorithm for least squares and adaptive algorithm implementation
The DSP for FPGA history
Lab 1: Using System Generator, ISE and ChipScope™ Tools
Use Xilinx System Generator within the Mathworks Simulink environment to implement simple DSP multiply/add/delay circuits and then synthesize, place and route and inspect the floor plan of some simple designs. ChipScope will be used with an example running on the FPGA board.
Arithmetic and CORDIC implementations
Lab 2: Multipliers, Adders, Dividers and CORDICs
Consider the many ways of implementing a multiplier (DSP48, constant coefficient, distributed, shift and add, etc.), and also looks at divider designs, and CORDIC implementations for calculation of sine, cosine, magnitude and other trigonometric calculations.
Digital Filters on FPGAs
Filter Retiming and Pipelining Methods
Lab 3: Digital Filter Design and Implementation
Look at filter designs in parallel and serial form, and also various techniques and methods for pipelining, multichannel filter implementation, and generally implementing efficient and low-cost filters with particular reference to decimation and interpolation filters. Audio examples will feature noise filtering using the FPGA board.
CIC and Moving Average Filters
Lab 4: CIC Filter Implementation
Implement CIC filter chains to understand the issues of word length growth, decimation/down-sampling, droop correction and applications at radio front ends (transmitters and receivers). Also implement filter receive chains featuring CICs, low pass, half band and other efficient filter implementations.
Numerically Controlled Oscillators (NCOs)
NCO Receiver Synchronization
Lab 5: Oscillator Design and Implementation
Implementation of numerically controlled oscillators using look-up-table methods and setting appropriate Spurious Free Dynamic Range (SFDR) and frequency accuracies. Also consider Xilinx cores for NCOs or Direct Digital Synthesis (DDS) and also using CORDIC-based oscillators and marginally stable IIR oscillators.
The Quadrature Amplitude Modulator (QAM) Tx and Rx
Lab 6: QAM Transceiver Design
A quadrature modulator transmitter and receiver will be implemented to modulate data to an IF carrier (around 3MHz), then receive using a quadrature receiver implementation. This lab will integrate the implementation of NCOs, standard digital filters, CICs, synchronizers in a single design.
Adaptive Signal Processing, Least Squares and the QR
Lab 7: QR Algorithm Implementation
A 5x5 (matrix) QR algorithm will be implemented (for least squares, linear system solvers, and general adaptive DSP implementations). A demonstration of using the QR for system identification will be set up in the lab, and a full CORDIC based design synthesized and placed and routed will be completed. This represents a high value, high complexity implementation.