Vivado® Design Suite delivers a SoC-strength, IP-centric and system-centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation. It comes in three editions:
- Vivado HL WebPack Edition
- Vivado HL Design Edition
- Vivado HL System Edition
The capabilities, limitations, and system requirements for the above editions can be found here.
Students can download the HL WebPack Edition free of charge from here and use on their own machine. Professors and researchers can also download the HL WebPack Edition to get acquainted with the suite. The HL WebPack Edition does not require license file and may be installed on multiple machines. During the HL WebPack Edition installation, cancel the installation process at the license file generation step. For teaching and research purpose, HL Design Edition or HL System Edition is often needed by professors and researchers. Xilinx University Program offers the full HL System Edition for purchase or donation. The HL Design Edition is NOT currently offered in the Xilinx University Program.
XUP has developed a number of workshops using Vivado Design suite. These workshops are typically two days long. All workshop materials are in English and consist of presentation slides and lab documents.
Professors can access the source documents and freely use the presentation material in their classroom for teaching purpose. They can modify, exclude the irrelevant slides they find to their course objectives, and add their own supplementary material. Thus they can extend the usability to a semester or quarter long period.
The lab source files are available for the students to carry out the labs. Lab solutions are only available to the professors.
|FPGA Design Flow using Vivado||Introductory||ZedBoard, ZYBO, Nexys4/DDR, NexysVideo, Basys3, PYNQ-Z1, PYNQ-Z2||2018x, 2016x, 2015x|
|Embedded System Design Flow on Zynq||Introductory||ZedBoard, ZYBO, PYNQ-Z1, PYNQ-Z2||2018x, 2015x, 2014x|
|High-Level Synthesis Flow on Zynq||Introductory||ZedBoard, ZYBO, PYNQ-Z1, PYNQ-Z2||2018x, 2017x, 2016x|
|System Design on Zynq using SDSoC||Introductory||ZedBoard, ZYBO, PYNQ-Z1, PYNQ-Z2||2018x, 2017x, 2016x|
|Advanced Embedded System Design on Zynq||Intermediate||ZedBoard, ZYBO, PYNQ-Z1, PYNQ-Z2||2018x, 2017x, 2016x|
|Embedded Linux on Zynq (Archived)||Intermediate||ZedBoard, ZYBO||2015x, 2014x, 2013x|
|System Design Flow on Zynq (Archived)||Intermediate||ZedBoard, ZYBO||2015x, 2014x, 2013x|
|Partial Reconfiguration Flow on Zynq||Intermediate||ZedBoard, ZYBO||2016x, 2015x, 2014x|
XUP Developed Teaching Material
Teaching Material Developed at Other Institutions