The Vivado Design suite supports 7-Series, Zynq, and UltraScale programmable families. It is developed to address the productivity bottlenecks in system-level design, integration, and implementation. The Vivado Design suite provides ease-of-use, system level integration capabilities, and new tools and methodologies, increasing overall productivity.
XUP has developed number of workshops using Vivado Design suite. These workshops are typically two days long. All workshop materials are in English and consist of presentation slides and lab documents. Professors can freely re-use the presentation material in their classroom for teaching purpose. There is no restriction to add, modify or delete the slides giving professors complete control and flexibility to incorporate the material according to the course objectives.
The lab source files are available for the students to carry out the labs. Lab solutions are only available to the professors.
|FPGA Design Flow using Vivado||Introductory||ZedBoard, ZYBO, Nexys4/DDR, NexysVideo, Basys3, PYNQ-Z1, PYNQ-Z2||2018x, 2016x, 2015x|
|Embedded System Design Flow on Zynq||Introductory||ZedBoard, ZYBO, PYNQ-Z1, PYNQ-Z2||2018x, 2015x, 2014x|
|High-Level Synthesis Flow on Zynq||Introductory||ZedBoard, ZYBO, PYNQ-Z1, PYNQ-Z2||2018x, 2017x, 2016x|
|System Design on Zynq using SDSoC||Introductory||ZedBoard, ZYBO, PYNQ-Z1, PYNQ-Z2||2018x, 2017x, 2016x|
|Advanced Embedded System Design on Zynq||Intermediate||ZedBoard, ZYBO, PYNQ-Z1, PYNQ-Z2||2018x, 2017x, 2016x|
|Embedded Linux on Zynq (Archived)||Intermediate||ZedBoard, ZYBO||2015x, 2014x, 2013x|
|System Design Flow on Zynq (Archived)||Intermediate||ZedBoard, ZYBO||2015x, 2014x, 2013x|
|Partial Reconfiguration Flow on Zynq||Intermediate||ZedBoard, ZYBO||2016x, 2015x, 2014x|