Upcoming Workshops Schedule
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There are no events scheduled for this region at this point in time
This tutorial will focus on the Adaptable Intelligent Engine (AIE) architecture and programming model, this compute engine is part of the Versal adaptive SoC platform. The AIE array is a tiled array of Very Long Instruction Word (VLIW) and Single Instruction Multiple Data (SIMD) processing elements that provide high compute density.
Workshop/Tutorial | Level | Boards |
Versions |
---|---|---|---|
Introduction to the Versal ACAP AI Engine and to its programming model | Introductory | VCK5000 | 2022.2 |
Compute Acceleration using Xilinx Vitis Development Tools | Introductory | AWS-F1, Alveo | 2021.1 |
Tile | Level | Boards | Versions |
---|---|---|---|
FPGA Design Flow using Vivado | Introductory | ZedBoard, ZYBO, Nexys4/DDR, NexysVideo, Basys3, PYNQ-Z1, PYNQ-Z2 | 2022x, 2018x, 2016x, 2015x |
Embedded System Design Flow on Zynq | Introductory | ZedBoard, ZYBO, PYNQ-Z1, PYNQ-Z2 | 2018x, 2015x, 2014x |
High-Level Synthesis Flow on Zynq | Introductory | ZedBoard, ZYBO, PYNQ-Z1, PYNQ-Z2 | 2018x, 2017x, 2016x |
Advanced Embedded System Design on Zynq | Intermediate | ZedBoard, ZYBO, PYNQ-Z1, PYNQ-Z2 | 2018x, 2017x, 2016x |
Partial Reconfiguration Flow on Zynq | Intermediate | ZedBoard, ZYBO | 2016x, 2015x, 2014x |
System Design on Zynq using SDSoC (Legacy) | Introductory | ZedBoard, ZYBO, PYNQ-Z1, PYNQ-Z2 | 2018x, 2017x, 2016x |
Embedded Linux on Zynq (Archived) | Intermediate | ZedBoard, ZYBO | 2015x, 2014x, 2013x |
Workshop/Tutorial | Level | Boards |
Versions |
---|---|---|---|
Digital Design using Vivado IPI | Introductory |
Nexys4/DDR, Basys3 | 2014.2 |
HDL Design | Introductory | Nexys4/DDR, Basys3 | 2013.3, 2015.1 |