XUP Workshops
Upcoming Workshops Schedule
ACAP: Introduction to the Versal ACAP AI Engine and to its programming model
This tutorial will focus on the Adaptable Intelligent Engine (AIE) architecture and programming model, this compute engine is part of the Versal Adaptive Compute Acceleration Platform (ACAP). The AIE array is a tiled array of Very Long Instruction Word (VLIW) and Single Instruction Multiple Data (SIMD) processing elements that provide high compute density.
16th January 2023
10:00-17:30 Central European Time
HiPEAC, Toulouse, France
No Events scheduled for now
There are no events scheduled for this region at this point in time
No Events scheduled for now
There are no events scheduled for this region at this point in time
Vitis Workshops
| Workshop/Tutorial | Level | Boards |
Versions |
|---|---|---|---|
| Compute Acceleration using Xilinx Vitis Development Tools | Introductory | AWS-F1, Alveo | 2021.1 |
Vivado Workshops
| Tile | Level | Boards | Versions |
|---|---|---|---|
| FPGA Design Flow using Vivado | Introductory | ZedBoard, ZYBO, Nexys4/DDR, NexysVideo, Basys3, PYNQ-Z1, PYNQ-Z2 | 2018x, 2016x, 2015x |
| Embedded System Design Flow on Zynq | Introductory | ZedBoard, ZYBO, PYNQ-Z1, PYNQ-Z2 | 2018x, 2015x, 2014x |
| High-Level Synthesis Flow on Zynq | Introductory | ZedBoard, ZYBO, PYNQ-Z1, PYNQ-Z2 | 2018x, 2017x, 2016x |
| Advanced Embedded System Design on Zynq | Intermediate | ZedBoard, ZYBO, PYNQ-Z1, PYNQ-Z2 | 2018x, 2017x, 2016x |
| Partial Reconfiguration Flow on Zynq | Intermediate | ZedBoard, ZYBO | 2016x, 2015x, 2014x |
| System Design on Zynq using SDSoC (Legacy) | Introductory | ZedBoard, ZYBO, PYNQ-Z1, PYNQ-Z2 | 2018x, 2017x, 2016x |
| Embedded Linux on Zynq (Archived) | Intermediate | ZedBoard, ZYBO | 2015x, 2014x, 2013x |
Vivado Teaching Material
| Workshop/Tutorial | Level | Boards |
Versions |
|---|---|---|---|
| Digital Design using Vivado IPI | Introductory |
Nexys4/DDR, Basys3 | 2014.2 |
| HDL Design | Introductory | Nexys4/DDR, Basys3 | 2013.3, 2015.1 |