The Versal Adaptive Compute Acceleration Platform (ACAP) is the latest generation technology in the Xilinx (now part of AMD) product line. ACAP devices feature: Adaptable Intelligent Engine (AIE), Programmable Logic (Adaptable Engine) and Processing System (Scalar Engine). These three Engines, tightly coupled with a Network-on-Chip, constitute a truly heterogeneous system in a single chip.
The AIE, a new type of compute element, is a tiled array of Very Long Instruction Word (VLIW) and Single Instruction Multiple Data (SIMD) processing elements that provides high compute density, helping overcome the decline of Moore’s law. At CES 2023, Lisa Su (AMD CEO) announced the integration of AIE on Ryzen 7040 AMD processors. More information about AIE here.
This tutorial will primarily focus on the Adaptable Intelligent Engine; however, we will briefly describe the ACAP architecture. This tutorial lays the foundations for understanding the capabilities of the Adaptable Intelligent Engine, its programming model, data movement and computation model (data flow architecture). On top of this, the hands-on session will allow attendees to explore the tools with fully functional examples that run in physical hardware on the cloud.
This tutorial will cover the following topics:
Some basic FPGA awareness would be an advantage, but is not required, although participants should have some knowledge of parallel processing concepts and/or parallel hardware. Familiarity with the C++ programming language would be an advantage. Familiarity with fix point arithmetic will be and advantages. Familiarity Vitis IDE software for application acceleration development flow will be an advantage.
AMD will provide remote access to cloud instances which will be enabled with tools and devices. Attendees must have their own laptop with reasonable screen size to effectively use the required software (Tablet, and Netbook type devices are not suitable).
The times in this agenda are tentative.
| Time | Topic |
|---|---|
| 9:00 – 10:30 | Overview of the Versal ACAP Architecture AI Engine Value Proposition Versal AI Engine Memory and Data Movement Introduction to the Versal AI Engine Architecture |
| 10:30 – 11:00 | Get connected to AWS and start Hands-on: vadd lab |
| 11:00 – 11:30 | Coffee Break |
| 11:30 – 12:00 | Hands-on: vadd lab |
| 12:00 – 13:00 | Scalar and Vector Data Types AI Engine APIs and Intrinsic Functions Window and Streaming Data APIs |
| 13:00 – 14:00 | Lunch |
| 14:00 – 14:45 | Hands-on: matrix mult lab |
| 14:45 – 16:00 | Versal ACAP Tool Flow VCK5000 Platform The Programming Model - Single Kernel Introduction to the Adaptive Data Flow Graph |
| 16:00 – 16:30 | Coffee Break |
| 16:30 – 17:15 | Vitis Analyzer The Programming Model - Multiple Kernels Using Graphs Versal DSP Library Overview AIE-ML Array Architecture |
| 17:15 – 18:00 | Hands-on: DSP Library lab |
Reference material can be found here: https://xilinx.github.io/xup_aie_training/
Instructors’ affiliation: AMD University Program, AECG at Advanced Micro Devices, Inc. (AMD)
Mario is a member of technical staff in the Adaptive and Embedded Computing Group, at AMD. As part of this role, he delivers training workshops for academics on the latest Xilinx tools and technologies. Mario completed his PhD in the Autonomous University of Madrid, which was focused on exploring High Level Synthesis tools in the context of networking.
Naveen is a member of technical staff in the Adaptive and Embedded Computing Group, at AMD. As part of this role, he delivers training workshops for academics on the latest Xilinx tools and technologies. Naveen received MS in Electrical and Computer Engineering from the University of New Mexico.
Hugo leads the AMD University Program and focuses on enabling the use of Adaptive Compute technologies for academic teaching, research, and entrepreneurial activities. Hugo has authored or co-authored over 65 patents and 25 academic research articles in the areas of virtual instrumentation, hardware/software interfacing, reconfigurable computing, graphical programming, models of computation, and system level design.
You can reach us at xup@amd.com
This tutorial will be held at the 50th International Symposium on Computer Architecture (ISCA 2023). Check the ISCA2023 site for more information. https://iscaconf.org/isca2023/
This is an in-person only event.
Orlando World Center Marriott
8701 World Center Dr Orlando, FL 32821
Check the ISCA2023 site for more information. https://iscaconf.org/isca2023/