Xilinx is now part ofAMDUpdated Privacy Policy

XUP PYNQ-Z2

z2
Overview

PYNQ- Python Productivity for Zynq

PYNQ is an open-source project from Xilinx® that makes it easier to use Xilinx platforms. Using the Python language and libraries, designers can exploit the benefits of programmable logic and microprocessors to build more capable and exciting electronic systems.

What is included?

  • The PYNQ-Z2 board featuring the ZYNQ XC7Z020-1CLG400C SoC

Additional Required Items

  • The pynq image and 8 GB SD Card
  • Micro-USB cable 
  • Ethernet cable 

Zynq-7000 SoC Features

  • Dual ARM® Cortex™-A9 MPCore™ with CoreSight™
  • 32 KB Instruction, 32 KB Data per processor L1 Cache
  • 512 KB unified L2 Cache
  • 256 KB On-Chip Memory
  • 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO
  • 2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO on-chip peripherals
  • 85K logic cells (13300 logic slices, each with four 6-input LUTs and 8 flip-flops)
  • 630 KB of fast block RAM
  • Four clock management tiles, each with phase-locked loop (PLL)
  • 220 DSP slices
  • Internal clock speeds exceeding 450MHz
  • 2x 12 bit, 1 MSPS On-chip analog-to-digital converter (XADC)
Hardware

Key Features

Feature Description
FPGA
  • Zynq-7000 SoC XC7Z020-1CLG400C
I/O Interfaces
  • USB-JTAG Programming circuitry
  • USB OTG 2.0
  • USB-UART bridge
  • One 10/100/1G Ethernet
  • HDMI Input
  • HDMI Output
  • I2S interface with 24bit DAC with 3.5mm TRRS jack
  • Line-in with 3.5mm jack
Memory
  • 512 Mbyte DDR3 with 16-bit bus @ 1050 Mbps
  • 128 Mbit Quad-SPI Flash
  • Micro SD card connector
Switches and LEDs
  • 2 Slide switches 
  • 2 RGB LEDs 
  • 4 LEDs
  • 4 Push-buttons 
Clocks
  • One 125 MHz for PL
  • One 50 MHz for PS
Expansion ports
  • 2 Pmod ports
    • 16 Total FPGA I/O (8 shared pins with Raspberry Pi connector)
  • 1 Arduino Shield connector
    • 24 Total FPGA I/O
    • 6 Single-ended 0-3.3V Analog inputs to XADC
  • Raspberry Pi connector
    • 28 Total FPGA I/O (8 shared pins with Pmod A port)
Tools & IP

Vivado

Vivado® ML is the Xilinx software suite for HDL and system-level design. Vivado includes a HDL simulator, IP Integrator for system-level integration, and tools for synthesis, implementation, bitstream generation and programming of Xilinx platforms.

Vivado Standard edition is a device limited version of the full Vivado enterprise edition and is free-of-charge and does not require a separate license.Licenses for the Vivado Enterprise edition which includes support for all Xilinx devices are available to universities from the XUP donation program.

You can select the free Vivado standard edition or the full Enterprise edition when you run the installer.

Download the Vivado installer

Vitis

Vitis™ is the Xilinx design software for targeting Alveo acceleration cards. It also includes software development tools for Xilinx embedded devices including the Zynq families. Vitis includes Vitis HLS, a C-based High-Level-Synthesis design tool that can be used standalone or from within Vitis for creating hardware accelerated kernel. Vitis is free of charge and does not require a separate license.

Download the Vitis installer

Contact XUP if you have any questions about Xilinx software or to discuss your requirements.

Purchasing and more information

Purchase from our partner: TUL

Visit the PYNQ-Z2 project page