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Designing FPGAs Using the Vivado Design Suite 2

Release Date:
May 2018
2 days

Quick Links

Key Documentation


Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs


Optional Videos


For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.

Course Description

This course shows you how to build an effective FPGA design using synchronous design techniques, using the Vivado® IP integrator to create a sub-system, using proper HDL coding techniques to improve design performance, and debugging a design with multiple clock domains.

Software Tools

  • Vivado System Edition 2018.1


  • Architecture: UltraScale™ and 7 series FPGAs*
  • Demo board (optional): Kintex®-7 FPGA KC705 board*

* This course focuses on the UltraScale and 7 series architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.


Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Identify synchronous design techniques
  • Build resets into your system for optimum reliability and design speed
  • Create a Tcl script to create a project, add sources, and implement a design
  • Describe and use the clock resources in a design
  • Create and package your own IP and add to the Vivado IP catalog to reuse
  • Use the Vivado IP integrator to create a block design
  • Apply timing exception constraints in a design as part of the Baselining procedure to fine tune the design
  • Describe how power analysis and optimization is performed
  • Describe the HDL instantiation flow of the Vivado logic analyzer

Course Outline

Lab Lecture Demo

Day 1

  1. 1.1
    UltraFast Design Methodology: Design Creation and Analysis Overview of the methodology guidelines covered in this course.
  2. 1.2
    Synchronous Design Techniques Introduces synchronous design techniques used in an FPGA design.
  3. 1.3
    Resets Investigates the impact of using asynchronous resets in a design.
  4. 1.4
    Register Duplication Use register duplication to reduce high fanout nets in a design.
  5. 1.5
    Scripting in Vivado Design Suite Project Mode Explains how to write Tcl commands in the project-based flow for a design.
  6. 1.6
    Clocking Resources Describes various clock resources, clocking layout, and routing in a design.
  7. 1.7
    I/O Logic Resources Overview of I/O resources and the IOB property for timing closure.
  8. 1.8
    Creating and Packaging Custom IP Create your own IP and package and include it in the Vivado IP catalog.

Day 2

  1. 2.1
    Using an IP Container Use a core container file as a single file representation for an IP.
  2. 2.2
    Designing with the IP Integrator Use the Vivado IP integrator to create the uart_led subsystem.
  3. 2.3
    Timing Constraints Editor Introduces the timing constraints editor tool to create timing constraints.
  4. 2.4
    Report Clock Networks Use report clock networks to view the primary and generated clocks in a design.
  5. 2.5
    Timing Summary Report Use the post-implementation timing summary report to sign-off criteria for timing closure.
  6. 2.6
    Clock Group Constraints Apply clock group constraints for asynchronous clock domains.
  7. 2.7
    Introduction to Timing Exceptions Introduces timing exception constraints and applying them to fine tune design timing.
  8. 2.8
    Power Analysis and Optimization Using the Vivado Design Suite Use report power commands to estimate power consumption.
  9. 2.9
    Configuration Process Understand the FPGA configuration process, such as device power up, CRC check, etc.
  10. 2.10
    HDL Instantiation Debug Probing Flow Covers the HDL instantiation flow to create and instantiate a VIO core and observe its behavior using the Vivado logic analyzer.
  11. 2.11
    Design Analysis Using Tcl Commands Analyze a design using Tcl commands.
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