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Designing FPGAs Using the Vivado Design Suite 3

Release Date:
June 2018
2 days

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Key Documentation


FPGA designers with intermediate knowledge of HDL and FPGA architecture and some experience with the Vivado® Design Suite


Optional Videos


For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.

Course Description

This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to debug your design using advanced capabilities of the Vivado logic analyzer.

Software Tools

  • Vivado Design or System Edition 2018.1


  • Architecture: UltraScale™ and 7 series FPGAs*
  • Demo board: Kintex®-7 FPGA KC705 board*

* This course focuses on the UltraScale and 7 series architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Employ good alternative design practices to improve design reliability
  • Define a properly constrained design
  • Apply baseline constraints to determine if internal timing paths meet design timing objectives
  • Optimize HDL code to maximize the FPGA resources that are inferred and meet performance goals
  • Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
  • Increase performance by utilizing FPGA design techniques
  • Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
  • Describe how to enable remote debug

Course Outline

Lab Lecture Demo

Day 1

  1. 1.1
    UltraFast Design Methodology: Implementation Introduces the methodology guidelines covered in this course.
  2. 1.2
    Vivado Design Suite Non-Project Mode Create a design in the Vivado Design Suite non-project mode.
  3. 1.3
    Baselining Use Xilinx-recommended baselining procedures to progressively meet timing closure.
  4. 1.4
    Pipelining Use pipelining to improve design performance.
  5. 1.5
    Inference Infer Xilinx dedicated hardware resources by writing appropriate HDL code.
  6. 1.6
    Revision Control Systems in the Vivado Design Suite Use version control systems with Vivado design flows.
  7. 1.7
    Timing Simulation Simulate the design post-implementation to verify that a design works properly on hardware.
  8. 1.8
    Synchronization Circuits Use synchronization circuits for clock domain crossings.

Day 2

  1. 2.1
    Report Clock Interaction Use the clock interaction report to identify interactions between clock domains.
  2. 2.2
    Report Datasheet Use the datasheet report to find the optimal setup and hold margin for an I/O interface.
  3. 2.3
    Dynamic Power Estimation Using Vivado Report Power Use an SAIF (switching activity interface format) file to determine accurate power consumption for a design.
  4. 2.4
    Configuration Modes Understand various configuration modes and select the suitable mode for a design.
  5. 2.5
    Netlist Insertion Debug Probing Flow Covers the netlist insertion flow of the debug using the Vivado logic analyzer.
  6. 2.6
    Sampling and Capturing Data in Multiple Clock Domains Overview of debugging a design with multiple clock domains that require multiple ILAs.
  7. 2.7
    JTAG to AXI Master Core Use this debug core to write/read data to/from a peripheral connected to an AXI interface in a system that is running in hardware.
  8. 2.8
    Debug Flow in an IP Integrator Block Design Insert the debug cores into IP integrator block designs.
  9. 2.9
    Remote Debugging Using the Vivado Logic Analyzer Use the Vivado logic analyzer to configure an FPGA, set up triggering, and view the sampled data from a remote location.
  10. 2.10
    Manipulating Design Properties Using Tcl Query your design and make pin assignments by using various Tcl commands.
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