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Designing with the Virtex-5 FPGA Family

Release Date:
June 2009
Level:
FPGA 3
Duration:
1 day

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Key Documentation

Audience

For those interested in Virtex-5 FPGA design training who have taken the Essentials of FPGA Design and Designing for Performancecourses.

Prerequisites

Register

For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.

Course Description

Interested in learning how to effectively utilize Virtex®-5 FPGA architectural resources? Targeted towards experienced Xilinx users who have already completed Essentials of FPGA Design and Designing for Performance, this course focuses on understanding as well as designing into several of the new and enhanced resources found in our newest device.

Topics covered include a Virtex-5 FPGA overview, the CLB, DCM and PLL, global and regional clocking techniques, memory, DSP and arithmetic logic, and source-synchronous resources. The resources available in the LXT and SXT platforms (EMAC, the PCI Express® architecture, and GTP transceivers) are also discussed. In addition, you will learn about the resources included in the TXT and FXT platforms (GTX transceivers and the PowerPC® processor). A combination of modules and labs allow for practical hands-on application of the principles taught.

Software Tools

  • Xilinx ISE® Design Suite: System Edition 11.1

Hardware Tools

  • Architecture: Virtex-5 FPGA*
  • Demo board: None*

* This course focuses on the Virtex-5 architecture. Check with your local Authorized Training Provider for specifics or other customizations.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe the 6-input LUT of the Virtex-5 FPGA
  • Specify the CLB arrangement in the Virtex-5 FPGA
  • Define the block RAM resources of the Virtex-5 FPGA
  • Differentiate the arithmetic logic resources of the DSP48E slice in the Virtex-5 FPGA
  • Identify the clocking resources of the Virtex-5 FPGA
  • Describe the additional features of the Virtex-5 LXT, SXT, TXT, and FXT FPGA platforms

Course Outline

Lab Lecture Demo

Day 1

  1. 1.1
    Introduction
  2. 1.2
    Virtex-5 FPGA Overview
  3. 1.3
    CLB Resources
  4. 1.4
    Clocking Resources
  5. 1.5
    Lab 1: Clocking Resources In this lab, you will use the Architecture Wizard to create a PLL core for instantiation in your design. You will then simulate and verify the PLL core.
  6. 1.6
    I/O Resources
  7. 1.7
    Memory Resources
  8. 1.8
    XtremeDSP Solution Resources
  9. 1.9
    Lab 2: DSP48E Resources n this lab, you will create a MACC and a loadable MACC by using the XtremeDSP™ solution (DSP48E) resource through the CORE Generator™ software. You will then compare the OPMODEs chosen by the CORE Generator software with the expected values.
  10. 1.10
    Virtex-5 LXT, SXT, FXT, and TXT FPGA Overview
  11. 1.11
    Lab 3: (Optional) DSP48E Resources The DSP48E resource in the Virtex-5 FPGA can also be utilized to create non-DSP functions in order to save slice resources. In this optional lab, you will create a multiplexer by using the XtremeDSP solution (DSP48E) resource through primitive instantiation. You will then simulate the resources to verify functionality.
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