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Designing with SystemVerilog

Release Date:
June 2017
2 days

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Key Documentation


FPGA designers and logic designers



For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.

Course Description

This comprehensive course is a thorough introduction to SystemVerilog constructs for design. This class addresses writing RTL code using the new constructs available in SystemVerilog. New data types, structs, unions, arrays, procedural blocks, and re-usable tasks, functions, and packages, are all covered. The information gained can be applied to any digital design. This course combines insightful lectures with practical lab exercises to reinforce key concepts.

In this two-day course, you will gain valuable hands-on experience. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently develop RTL designs.

Software Tools

  • Vivado® Design or System Edition 2017.1
  • Questa Sim Prime Simulator 10.5b


  • Architecture: N/A*
  • Demo board: Kintex® UltraScale™ FPGA KCU105 board or Kintex-7 FPGA KC705 board*

* This course does not focus on any particular architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this training, you will know how to:

  • Describe the features and benefits of using SystemVerilog for RTL design
  • Identify the new data types supported in SystemVerilog
  • Use an enumerated data type for coding a finite state machine (FSM)
  • Explain how to use structures, unions, and arrays
  • Describe the new procedural blocks and analyze the affected synthesis results
  • Define the enhancements and ability to reuse tasks, functions, and packages
  • Identify how to simplify module definitions and instantiations using interfaces
  • Examine how to efficiently code in SystemVerilog for FPGA design simulation and synthesis
  • Target and optimize Xilinx FPGAs by using SystemVerilog
  • Synthesize and analyze SystemVerilog designs with the Vivado Design Suite
  • Download a complete SystemVerilog design to an evaluation board

Course Outline

Lab Lecture Demo

Day 1

  1. 1.1
    Introduction to SystemVerilog
  2. 1.2
    Data Types
  3. 1.3
    Demo: SystemVerilog Integer Data Types
  4. 1.4
    Lab 1: SystemVerilog Data Types Use enumerated data types to build a finite state machine and perform synthesis to analyze the results.
  5. 1.5
    Structures, Unions, and Arrays
  6. 1.6
    Lab 2: Structures and Unions Learn about packed and unpacked structures and unions and how to access their members.
  7. 1.7
    Additional Operators in System Verilog
  8. 1.8
    Procedural Statements and Flow Control
  9. 1.9
    Lab 3: always_ff and always_comb Procedural Blocks Learn to use the new procedural blocks always_comb, always_ff, and always_latch to produce the intended synthesized results.

Day 2

  1. 2.1
    Functions, Tasks, and Packages
  2. 2.2
    Lab 4: Functions, Tasks, and Packages Create a new package and import that package into the module.
  3. 2.3
  4. 2.4
    Targeting Xilinx FPGAs
  5. 2.5
    Lab 5: Interfaces and Design Download Use an interface to simplify the module inputs and outputs. Download and verify the design in-circuit.
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