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Xilinx Partial Reconfiguration Tools & Techniques

Release Date:
November 2017
Level:
FPGA 4
Duration:
2 days

Key Documentation

Audience

Digital designers who have a working knowledge of HDL (VHDL or Verilog) and the Xilinx design methodology and who want to learn partial reconfiguration techniques.

Prerequisites

Register

For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.

Course Description

This course demonstrates how to use the Vivado® Design Suite to construct, implement, and download a Partially Reconfigurable (PR) FPGA design. You will gain a firm understanding of PR technology and learn how successful PR designs are completed. You will also identify best design practices and understand the subtleties of the PR design flow. This course also demonstrates how to use thee PR controller and PR decoupler IP in the PR process. You will also gain an understanding of PR implementation in an embedded system environment.

This course covers both the tool flow and mechanics of successfully creating a PR design. This course also covers both UltraScale™ and 7 series architecture design requirements, recommendations, and expectations for PR systems. In addition, it describes several techniques focusing on appropriate coding styles for a PR system as well as system-level design considerations and practical applications. You will also identify techniques to debug PR designs.

Software Tools

  • Vivado Design or System Edition 2017.3

Hardware

  • Architecture: UltraScale and 7 series FPGAs*
  • Demo board: Kintex® UltraScale FPGA KCU105 board, Kintex-7 FPGA KC705 board, and ZedBoard**

* This course focuses on the UltraScale and 7 series architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

** The UltraScale architecture versions of the "Using the PRC IP in a Partial Reconfiguration Design" lab and the "Using ILA Cores to Debug Partial Reconfiguration Designs" lab are not available because of QSPI and PRC issues on the KCU105 board. These two labs support only the 7 series architecture. The "Partial Reconfiguration in Embedded Systems" lab requires a ZedBoard for implementation.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Build and assemble a Partially Reconfigurable system (UltraScale, 7 series, and Zynq® devices)
  • Define PR regions and reconfigurable modules with the Vivado Design Suite
  • Generate the appropriate full and partial bitstreams for a PR Design
  • Use the ICAP and PCAP components to deliver the Partially Reconfigurable systems
  • Identify how Partial Reconfiguration affects various silicon resources, including block RAM, IOBs, fabric, clock buffers, and MGTs
  • Implement a Partial Reconfiguration system using the following techniques:
    • Direct JTAG connection
    • Floorplanning
    • Timing constraints and analysis
  • Implement a PR system using the PRC IP
  • Implement a PR system in an embedded environment
  • Debug PR designs

Course Outline

Lab Lecture Demo

Day 1

  1. 1.1
    Introduction to Partial Reconfiguration
  2. 1.2
    Demo: Introduction to Partial Reconfiguration
  3. 1.3
    Partial Reconfiguration Flow
  4. 1.4
    Lab 1: Partial Reconfiguration Tool Flow Illustrates the basic Vivado Design Suite Partial Reconfiguration flow. At the completion of this lab, you will download a partial bitstream to the demo board via the JTAG connection.
  5. 1.5
    Lab 2: Partial Reconfiguration Project Flow Illustrates the basic Vivado Design Suite Partial Reconfiguration flow. At the completion of this lab, you will download a partial bitstream to the demo board via the JTAG connection.
  6. 1.6
    Lab 3: Floorplanning the PR Design Illustrates how to create efficient Pblocks for a Partial Reconfiguration design. At the end of this lab, you will understand the impact of the SNAPPING_MODE property for a Pblock.
  7. 1.7
    Partial Reconfiguration Design Considerations
  8. 1.8
    Optional: FPGA Configuration Overview
  9. 1.9
    Partial Reconfiguration Bitstreams
  10. 2.0
    Demo: Partial Reconfiguration Controller (PRC) IP
  11. 2.1
    Lab 4: Using the Partial Reconfiguration Controller in a PR Design Illustrates using the PRC IP and hardware triggers to manage partial bitstreams.

Day 2

  1. 2.2
    Partial Reconfiguation: Managing Timing
  2. 2.3
    Lab 5: Partial Reconfiguration Timing Analysis and Constraints Shows how area groups and Reconfigurable Partitions affect design performance.
  3. 2.4
    Partial Reconfiguration in Embedded Systems
  4. 2.5
    Lab 6: Partial Reconfiguration in Embedded Systems Illustrates implementing PR designs in an embedded environment.
  5. 2.7
    Debugging Partial Reconfiguration Designs
  6. 2.8
    Lab 7: Debugging a Partial Reconfiguration Design Demonstrates using ILA cores to debug PR designs and shows which signals to monitor during debugging.
  7. 2.9
    Partial Reconfiguration Design Recommendations
  8. 3.0
    PCIe Core and Partial Reconfiguration
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