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SDSoC Development Environment and Methodology

Release Date:
August 2017
Level:
Embedded 2
Duration:
1 Day

Quick Links

Key Documentation

Audience

Anyone interested in quickly adding hardware acceleration to a software system.

Prerequisites

  • Understanding of Zynq®-7000 architecture (with emphasis on ACP, HP ports, and internal routing)
  • Comfort with the C programming language
  • Familiarity with the Vivado® Design Suite, Vivado HLS tool, and Xilinx SDK

Register

For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.

Course Description

This one-day course is structured to help designers new to the SDSoC™ development environment to quickly understand the full "end-user" tool flow to create accelerated systems. The focus is on utilizing the tools to accelerate an existing design at the system architecture level, not on the optimization of the accelerator microarchitectures.

Several optional modules are provided to quickly provide students with the necessary background on both hardware and software.

Software Tools

  • SDx™ development environment 2017.1

Hardware

  • Architecture: Zynq-7000 All Programmable SoC*
  • Demo board: Zynq-7000 All Programmable SoC ZC702 or ZedBoard*

* This course focuses on the Zynq-7000 All Programmable SoC. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Identify candidate functions for hardware acceleration by using the TCF profiling tool
  • Use the System Debugger's capabilities to control the execution flow and examine memory and variables during a debug session
  • Move designated software functions to hardware and estimate the performance of the accelerator and the effect on the entire system
  • Use the hardware/software event trace to understand the performance of an application given the workload, hardware/software partitioning, and system design choices

Course Outline

Lab Lecture Demo

Day 1

  1. 1.1
    Zynq AP SoC Architecture Support for Accelerators [Optional] Discusses the relevant aspects of the Zynq All Programmable SoC architecture for accelerator design. The focus is on AXI ports and protocols, system latency, and memory utilization.
  2. 1.2
    Software Overview [Optional] Provides a thorough understanding of how the integrated design environment works, including how the compiler and linker behave, basics of makefiles, DMA usage, and variable scope.
  3. 1.3
    Introduction to the SDSoC Tool Introduces the purpose, underlying structures, and basic functionality of the SDSoC development environment.
  4. 1.4
    SDSoC Tool Flow Explains the complete development flow of the SDSoC integrated development environment (IDE).
  5. 1.5
    Application Debugging Through the use of the System Debugger, students will learn how to follow the control flow in an executing application and see the effects of the code on memory to successfully debug software issues.
  6. 1.6
    Application Profiling Profiling is the process that identifies how the processor is spending its time. Through profiling, the user can quickly identify which functions must be optimized or moved to hardware to satisfy the performance requirements.
  7. 1.7
    Understanding Estimations in the SDSoC Tool Once a function is moved to hardware, questions remain: Will the accelerator fit in hardware? Will it fun fast enough? Estimations can provide the answers.
  8. 1.8
    QEMU Emulation Describes how to use the emulation feature in the SDx IDE.
  9. 1.9
    Hardware/Software Event Tracing Hardware/software event tracing helps users understand the performance of their application given the workload, hardware/software partitioning, and system design choices. Such information helps the user to optimize and improve system implementation.
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