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Verification with SystemVerilog

Release Date:
June 2017
Level:
FPGA 1
Duration:
2 days

Quick Links

Key Documentation

Audience

Hardware and verification engineers

Prerequisites

Recommended

Register

For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.

Course Description

This comprehensive course is a thorough introduction to SystemVerilog constructs for verification. This class addresses writing testbenches to verify your design under test (DUT) utilizing the new constructs available in SystemVerilog. Object-oriented modeling, new data types, re-usable tasks and functions, randomization, code coverage, assertions, and the Direct Programming Interface (DPI) are all covered. The information gained can be applied to any digital design verification approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts.

In this two-day course, you will gain valuable hands-on experience. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently verify designs.

Software Tools

  • Questa Sim Prime Simulator 10.5b
  • Vivado® Design or System Edition 2017.1

Hardware

  • Architecture: N/A*
  • Demo board: None*

* This course does not focus on any particular architecture. Check with your local Authorized Training Provider for specifics or other customizations.

Skills Gained

After completing this training, you will know how to:

  • Describe the advantages and enhancements to SystemVerilog to support verification
  • Define the new data types available in SystemVerilog
  • Analyze and use the improvements to tasks and functions
  • Discuss and use the various new verification building blocks available in SystemVerilog
  • Describe object-oriented programming and create a class-based verification environment
  • Explain the various methods for creating random data
  • Create and utilize random data for generating stimulus to a DUT
  • Identify how SystemVerilog enhances functional coverage for simulation verification
  • Utilize assertions to quickly identify correct behavior in simulation
  • Identify how the direct programming interface can be used with C/C++ in a verification environment

Course Outline

Lab Lecture Demo

Day 1

  1. 1.1
    Introduction to SystemVerilog for Verification
  2. 1.2
    Data Types
  3. 1.3
    Tasks and Functions
  4. 1.4
    Lab 1: Implementing Tasks and Functions Use a task and function to provide input data for a DUT and perform simulation.
  5. 1.5
    SystemVerilog Verification Building Blocks
  6. 1.6
    Lab 2: Connecting the Testbench to the DUT Utilize new SystemVerilog verification building blocks to connect the input data to the DUT.
  7. 1.7
    Object-Oriented Modeling
  8. 1.8
    Lab 3: Object-Oriented Modeling Use object-oriented programming concepts to create a class for enhancing the verification of the DUT.

Day 2

  1. 2.1
    Randomization
  2. 2.2
    Lab 4: Randomization Create random data as input into the DUT to fully validate the design.
  3. 2.3
    Coverage
  4. 2.4
    Lab 5: Coverage Create and use a coverage group to validate the code coverage for the DUT. Make adjustments and again validate the coverage.
  5. 2.5
    Assertions
  6. 2.6
    Lab 6: Assertions Create an assertion to validate all possible conditions are verified for the DUT.
  7. 2.7
    Direct Programming Interface
  8. 2.8
    Demo: Direct Programming Interface
  9. 2.9
    Inter Process Communication
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