This course introduces the Versal™ ACAP architecture and design methodology. This is a one-day version of the Designing with the Versal ACAP: Architecture and Methodology OnDemand course available for purchase.
The following are the virtual online sessions delivered by live instructors in Greater China over the course of two days in March 2021.
The lab instructions and lab files for this course are available for download here.
Offers background information and an overview of the Xilinx Versal ACAP portfolio.
|2||Xilinx Global Training & Enablement
Reviews the training solutions offered by Xilinx and our global network of Authorized Training Providers.
|3||Architecture and Overview
Provides a high-level overview of the Versal architecture, illustrating the various engines available in the Versal architecture.
|4||Design Tool Flow
Maps the various engines in the Versal architecture to the tools required and describes how to target them for final image assembly.
Reviews the Cortex™-A72 processor APU and Cortex-R5 processor RPU that form the Scalar Engine. The platform management controller (PMC), processing system manager (PSM), I/O peripherals, and PS-PL interfaces are also covered.
|6||NoC Introduction and Concepts
Covers the reasons to use the network on chip, its basic elements, and common terminology.
|1||Recap of Day One
Reviews day one.
|2||NoC Introduction and Concepts Demo
Provides an instructor-led demonstration on customizing the Versal ACAP NoC IP.
Discusses the AI Engine array architecture, terminology, and AIE interfaces.
Describes the I/O bank, SelectIO™ interface, and I/O delay features.
|5||System Simulation: Part One and Part Two (demo)
Explains how to perform system-level simulation in a Versal ACAP design.
Covers what application partitioning is and how the mapping of resources based on the models of computation can be performed.