Aurora is a scalable, lightweight, link-layer protocol that is used to move data across point-to-point serial links. It is an open protocol and is free of charge. It provides a transparent interface to the physical serial links, allowing upper layers of proprietary or industry-standard protocols to easily use these high-speed serial links.
Aurora is a very efficient low-latency protocol that uses the least possible amount of logic while offering a rich, highly configurable feature set. Aurora increases bandwidth through bonded lanes. Aurora also requires little time to integrate in to existing user designs.
Aurora is a free and open standard. The source code generated by the Xilinx tools may be used at no additional charge on Xilinx devices under the terms of the Xilinx End User License Agreement. Implementing Xilinx generated Aurora source code on an ASIC/ASSP is not free of charge and requires a separate license agreement.
|Xilinx Solutions for Aurora: Benefits by Market|
|Wired networking and telecom and wireless||Proprietary Backplane||Easy encapsulation of Ethernet and other protocols|
|Servers and storage||FPGA to FPGA communication||Maximum Bandwidth|
|Test and measurement||FPGA to FPGA communication||Adjustable User Flow Control|
|Industrial, scientific and medical||Board-to-board and FPGA to FPGA applications||
Support for simplex modes
|Audio, visual, broadcast||Board-to-board protocol||Large number of bonded lanes|
|Consumer||Full Mesh FPGAs||Unlimited Frame size/flexible framing|
|Xilinx Solutions for Aurora: By IP|
|Aurora IP||FPGA Device||Technical Documents|
|Aurora 64B/66B||Kintex® UltraScale™ / Virtex® UltraScale / Zynq®-7000 / Kintex-7 / Virtex-7 / Virtex-6 / Virtex-5||Documentation|
|Aurora 8B/10B||Kintex UltraScale / Virtex UltraScale / Zynq-7000 / Artix®-7 / Kintex-7 / Virtex-7 / Virtex-6 / Virtex-5 / Spartan®-6||Documentation|
Aurora can be used in any application that requires serial point to point connectivity. Aurora can be applied where an inexpensive, high-performance link layer with little resource consumption is required, saving many hours of work for users who were considering developing their own MGT protocols. Some of the popular applications are listed here.
|Data Flow||Full-duplex, TX-only
|Full-duplex offers both side communication between the channel partners
Simplex cores provide communication to the respective side of the channel partner
|Reduced logic for simplex|
Framing interface is based on AXI4-Stream with framing delimiters and controls
Streaming interface is a light weight AXI4-Stream based with no framing delimiters
|Reduced logic for Streaming core|
|Number of Lanes||1 to 16||GUI based GT selection||Bonded lanes offer uniform skew across lanes|
|Line Rate||500Mbps to 13.1Gbps||GT Settings configured automatically||Any GT supported line rate supported|
|Lane Width||2/4 bytes - Aurora 8B10B
8 bytes - Aurora 64B66B
|User interface width||Select based on user interface requirement|
|Scrambling||Payload only - Aurora 8B10B
Payload + controls - aurora 64B66B
|Scrambles based on standard polynomial||Reduced EMI for high lane rates|
|GT Reference Clock||Select from available values||Calculated based on line rate and GT lane width|
|Clock Correction||GND for synchronous clocking||CC characters transmitted periodically to compensate clock differences||Suitable for chip-to-chip, board-to-board, and backplane applications|
|Data Integrity Check||CRC16, CRC32 or none||Standard CRC polynomial used for data integrity check||Upper layers can take action|
|Flow control||User flow control, Native Flow control, User-K||High priority flow controls can be inserted between data. combinations of flow controls allowed based on requirement||Optional logic to insert high-priority data or control information|
|Hot Plug||Hot plug circuitry for dynamic disconnect and reconnect of the cables||Automatically detects and re-initializes the channel|
|DRP Interface||Native or AXI4-Lite||DRP interface to update GT settings||On-the-fly-updates to GT settings|
|User Interface||AXI4-Stream||Standard interface provides all required controls for the frame||Standard interface by ARM|
Aurora can also be supported in Application Specific Integrated Circuits (ASIC) through a license of the Xilinx Aurora core. To support ASIC applications, Xilinx provides a Bus Functional Model (BFM).
The ABFM models the behavior of the Aurora protocol and can be used as a reference model to check the compliance of the design with the Aurora Protocol. The ABFM can also generate stimulus for and to monitor the response of an Aurora interface design, which is referred to as the device under test (DUT). The Aurora BFMs are available for both the Aurora 8B10B Protocol and the Aurora 64B66B Protocol. The ABFM provides parameterization of the protocol parameters (number of lanes, interface width, etc..) and that can be used to test any implementation of the Aurora protocol.
The ABFMs provides flexibility, a clean room implementation of Aurora to verify the DUT or an ASSP/ASIC compliance with Aurora protocol. The ABFM can be easily integrated into an existing verification environment specifically designed to test the DUT. Once the ABFM is integrated into the verification environment, it can communicate with the DUT using a programming language interface (PLI) for Verilog environments or a foreign language interface (FLI) for VHDL + Modelsim environment or a VHPI interface for VHDL + NCSIM environment. The PLI, FLI and VHPI contain transaction based calls that are used to establish communication between the DUT and ABFM.
For information on the Aurora protocol specification, ASIC licensing and pricing, or for BFM availability, contact your local sales person or Xilinx Aurora Marketing.