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AR# 10020

14.x Constraints - How do I apply an OFFSET constraint for individual I/Os?

Description

How do I apply an OFFSET constraint with individual nets or I/Os?

Solution


OFFSET Overview

Figure 1a - OFFSET Overview in the overall board
Figure 1a - OFFSET Overview in the overall board


The OFFSET constraint specifies external data and external clock relationships. The calculation of the constraint uses the Data and Clock delay. The paths to and from IOB flip-flops are fixed delay, but they are covered by this constraint.

Figure 1b - OFFSETS cover these paths inside the FPGA
Figure 1b - OFFSETS cover these paths inside the FPGA


For more details on timing constraints, please see the Timing Constraints User Guide:http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_1/ug612.pdf




OFFSET IN AFTER



Figure 2a - OFFSET IN AFTER overall board view
Figure 2a - OFFSET IN AFTER overall board view


Example UCF specification:

NET CLK PERIOD = 20;
NET DI_PAD OFFSET = IN 15ns AFTER CLK_PAD;

Figure 2b - OFFSET IN waveform of data and the clock
Figure 2b - OFFSET IN waveform of data and the clock


The previous example indicates that the data arrives at point (D) 15 ns after clock arrives at (C). In this example, the FPGA has 5 ns left over to route and register DATA_IN. The OFFSET constraints are in reference to pads, so DATA_IN and CLK are not valid offset points.

Figure 2c - OFFSET IN AFTER design view
Figure 2c - OFFSET IN AFTER design view


The following example is the constraint in the timing report:

================================================================

Timing constraint: COMP "DI_PAD" OFFSET = IN 15 nS AFTER COMP "CLK_PAD" ;

1 item analyzed, 0 timing errors detected.

Maximum allowable offset is 19.442 ns.

--------------------------------------------------------------------------------------------------------------------------------

Slack:

4.444ns path DI_PAD to DATA_FD relative to
2.159ns delay constraint CLK_PAD to DATA_FD and
2.715ns delay constraint DI_PAD to DATA_FD and
5.000ns offset DI_PAD to CLK_PAD

OFFSET OUT BEFORE

Figure 3a - OFFSET OUT BEFORE overall board view
Figure 3a - OFFSET OUT BEFORE overall board view


Example UCF specification:

NET CLK PERIOD = 20;
NET DO_PAD OFFSET = OUT 5ns BEFORE CLK_PAD;

Figure 3b - OFFSET OUT waveform of data and the clock
Figure 3b - OFFSET OUT waveform of data and the clock


This means that data must be valid at point (D) 5 ns before clock arrives at (C). In this example, the FPGA has 15 ns to register and route data off the chip.

Figure 3c - OFFSET OUT BEFORE design view
Figure 3c - OFFSET OUT BEFORE design view


The following example is the constraint in the timing report:

================================================================

Timing constraint: COMP "DO_PAD" OFFSET = OUT 5 nS BEFORE COMP "CLK_PAD" ;

1 item analyzed, 0 timing errors detected.

Maximum allowable offset is 10.061 ns.

--------------------------------------------------------------------------------------------------------------------------------

Slack:

5.061ns path CLK_PAD to DO_PAD relative to
2.159ns delay CLK_PAD to DATA_OUT and
7.780ns delay DATA_OUT to DO_PAD and
15.000ns offset CLK_PAD to DO_PAD

(Note that it takes 7.78 ns to go from DATA_OUT to the output pad.)

With clock delay, the total output delay is 9.939 ns.

OFFSET IN BEFORE

Figure 4a - OFFSET IN BEFORE overall board view
Figure 4a - OFFSET IN BEFORE overall board view


Example UCF specification:

NET CLK PERIOD = 20;
NET DI_PAD OFFSET = IN 5ns BEFORE CLK_PAD;

Figure 4b - OFFSET IN waveform of data and the clock
Figure 4b - OFFSET IN waveform of data and the clock


This means that data is valid at point (D) 5 ns before the clock arrives at (C), In this example, the FPGA has 5 ns to route and register DATA_IN. This specification tells the tools directly how much routing/setup is available.

Figure 4c - OFFSET IN BEFORE design view
Figure 4c - OFFSET IN BEFORE design view


The following example is the constraint in the timing report:

================================================================

Timing constraint: COMP "DI_PAD" OFFSET = IN 5 nS BEFORE COMP "CLK_PAD" ;

1 item analyzed, 0 timing errors detected.

Minimum allowable offset is 0.558 ns.

-------------------------------------------------------------------------------------------------------------------------------

Slack:

4.442ns path DI_PAD to DATA_FD relative to
2.671ns delay constraint DI_PAD to DATA_FD and
2.113ns delay constraint CLK_PAD to DATA_FD and
5.000ns offset DI_PAD to CLK_PAD

OFFSET OUT AFTER

Figure 5a - OFFSET OUT AFTER overall board view
Figure 5a - OFFSET OUT AFTER overall board view


Example UCF specification:

NET CLK PERIOD = 20;
NET DO_PAD OFFSET = OUT 15ns AFTER CLK_PAD;

Figure 5b - OFFSET OUT waveform of data and the clock
Figure 5b - OFFSET OUT waveform of data and the clock


This means that data must be valid at point (D) 15 ns after clock arrives at (C). In this example, the FPGA has 15 ns to register and route data off the chip.

Figure 5c - OFFSET OUT AFTER design view
Figure 5c - OFFSET OUT AFTER design view


The following example is the constraint in the timing report:

================================================================

Timing constraint: COMP "DO_PAD" OFFSET = OUT 15 nS AFTER COMP "CLK_PAD" ;

1 item analyzed, 0 timing errors detected.

Minimum allowable offset is 10.289 ns.

------------------------------------------------------------------------------------------------------------------------------

Slack:

4.711ns path CLK_PAD to DO_PAD relative to
2.110ns delay CLK_PAD to DATA_OUT and
8.179ns delay DATA_OUT to DO_PAD and
15.000ns offset CLK_PAD to DO_PAD
AR# 10020
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article
Tools
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