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AR# 10178

LogiCORE PCI - A PCI Core does not respond to I/O or memory transactions as a target (DEVSEL is never asserted)

Description

General Description:

After I assign a valid address to BARx, my Xilinx PCI device still does not respond to memory or I/O transactions as a target.

Solution

Memory Space Access

The Memory Space bit in the Command/Status Register needs to be set by the host system before the Xilinx PCI device will respond to memory space accesses.

I/O Space Access

The I/O Space bit in the Command/Status Register must be set by the host system before the Xilinx PCI device will respond to I/O space accesses.

The Command/Status register is located at offset 04h in the Configuration Space Header as illustrated below:

Configuration Space Header Command Register Mapping
Configuration Space Header Command Register Mapping

AR# 10178
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article