The Virtex-II pin-out data/package file does not list the pins in the die pad order with the VCCO/GND pads between the I/O. (Virtex/Virtex-E pin-out tables do have this information.)
For example, compare the following two package files:
(This Virtex-II file does NOT include the VCCO/GND pad locations.)
(This shows where VCCO/GND are inserted among the pins.)
The Simultaneously Switching Output Guidelines for Virtex-II in the "Virtex-II Platform FPGA User Guide" (see link below) list the following:
- Maximum number of simultaneously switching outputs per Power/Ground pin in Table 2-37
- Equivalent Power/Ground pairs per bank in Table 2-38
Select Design Considerations -> Using Single-Ended Select I/O Ultra Resources -> Design Considerations -> Simultaneous Switching Output (SSO) Guidelines.
How do I follow the SSO guidelines and distribute the outputs properly without information on the location of the Power/Ground pairs among the I/O?
The "equivalent" Power/Ground pairs are not the physical number of Power/Ground pairs. Physically, many more Power/Ground pairs are located between the I/Os to ensure short paths to Power and Ground. However, the package parasitic and inductance, as well as process variation, also contribute to the overall effect of SSO. The "equivalent" Power/Ground pair numbers are generated with all of these effects taken into consideration.
To determine the maximum SSO per bank, use the two tables with the correct I/O standard. For example, if you are using GTL with a maximum SSO of 4 per Power/Ground pair, and 2v1000fg256 with 3 equivalent Power/Ground pairs per bank, your maximum SSO per bank is: 3 x 4 = 12.
There are no further restrictions on the placement of I/Os within a bank, and the physical placement of Power/Ground on the die is NOT needed to follow the SSO guideline. Also, it is important to note that a good decoupling scheme is A MUST. Reference (Xilinx XAPP623): "Power Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors" for more information on PDS decoupling.