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AR# 12325

12.1 Known Issue - Timing/PAR - Error: "A Xilinx application has run out of memory"


When I run my EDIF and UCF through implementation, the following error occurs during the initial timing analysis:

"A Xilinx application has run out of memory."


To work around this problem, consolidate individual "FROM:TO" constraints into a smaller number of "FROM:TO" constraints. If several FROM:TO constraints have a common source group or destination group, they can be combined. This can be done by creating a new time group for either the sources or the destination (the time groups that are not in common) and creating a new FROM:TO constraint.

You can also consolidate Net OFFSET constraints into Group OFFSET constraints; the key to avoiding this problem is to consolidate as many OFFSET constraints as possible.

This issue is scheduled to be fixed in the next major design tools release (after 11.1).
AR# 12325
Date 05/13/2012
Status Active
Type Known Issues
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
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