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AR# 13349

Virtex-II/Virtex-II Pro, DCM - The use of negative, FIXED-mode phase shift requires a work-around or a positive PHASE_SHIFT value (DPS)

Description

The use of a negative, FIXED-mode phase shift with the Virtex-II DCM requires a minor modification to the clock muxing. 

Specifically, CLKIN must be used to drive CLKFB while the DCM is in reset (when the RST signal is held High or during the startup sequence after configuration). 

The diagram and example Verilog and VHDL code below illustrate the implementation of this simple modification. 

This modification is NOT required for any positive phase shifting or for any variable-mode phase shifting.

Note: 

The requirement applies to any Virtex-II/ Virtex-II Pro DCM using FIXED-mode phase, regardless of whether the RST of DCM is connected to a user signal. 

RST must be held High for at least three clock cycles.

This issue applies to all Virtex-II devices.

This does not apply to Virtex-4 DCM's. For more information on this warning and Virtex-4 DCM's, please see (Xilinx Answer 22095).

This issue is fixed in the Virtex-II Pro devices listed in the table below:

13349-1.gif



Solution

The following diagram illustrates the clock-muxing modification:

Clock Muxing for Negative PHASE_SHIFT Value

Note: PAR might report a warning that the IBUFG (CLKIN)-to-BUFGMUX connection is not an optimal connection and will not use the fast connection between the two components. 

You can safely ignore this warning. In this case, a dedicated connection is not necessary for the IBUFG-BUFGMUX connection.


Verilog Example

//DCM instantiation

DCM U_DCM ( .CLKIN(clkin), .CLKFB(clk0_new), .RST(rst), .CLK0(clk0), .LOCKED(locked) );

//BUFGMUX instantiation

BUFGMUX U_BUFGMUX ( .O(clk0_new), .I0(clk0), .I1(clkin), .S(rst) );


VHDL Example

-- DCM instantiation --

U_DCM: DCM port map ( CLKIN => clkin,

CLKFB => clk0_new,

DSSEN => '0',

PSCLK => '0',

PSINCDEC => '0',

RST => rst,

CLK0 => clk0,

LOCKED => locked);

-- BUFGMUX instantiation --

U_BUFGMUX: BUFGMUX( I0 => clk0

I1 => clkin,

O => clk0_new);


Alternative Work-Around Using Positive Phase Shift

You can also work around this problem by using an equivalent positive PHASE_SHIFT value. Given the current data sheet specification of FINE_SHIFT_RANGE = 10 ns, this restriction begins to have an effect for input frequencies below 100 MHz (input periods larger than 10 ns).

Given the equation:

phase shift = (PS/256) * PeriodCLKIN

For a 10 ns input clock period:

VARIABLE mode: -128 <= PS <= 128

FIXED mode: 0 <= PS <= 255 (full range)

For a 20 ns input clock period:

VARIABLE mode: -64 <= PS <= 64

FIXED mode: 0 <= PS <= 128

For a 40 ns input clock period:

VARIABLE mode: -32 <= PS <= 32

FIXED mode: 0 <= PS <= 64

In either FIXED or VARIABLE mode, you can extend the range by choosing one of the following:

- CLK90, CLK180, or CLK270 rather than CLK0

- CLK2X180 rather than CLK2X

- CLKFX180 rather than CLKFX

Even at 25 MHz (a 40 ns period), the FIXED mode coupled with these CLK* phases allows shifting throughout the entire input clock period range. Refer to the following figure:

Fixed Phase Shift Example

Furthermore, the phase-shifting (DPS) function in DCM requires the CLKFB for delay adjustment. For more information, see the Virtex-II or Virtex-II Pro User Guide: Design Considerations -> Using the Digital Clock Manager (DCM) -> Phase Shifting:


Virtex-II

http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=/User+Guides/FPGA+Device+Families/Virtex-II/&iLanguageID=1


Virtex-II Pro

1. Go to:

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=User+Guides
2. Select Virtex-II Pro under "FPGA Device Families."

3. Select Virtex-II Pro Platform FPGA User Guide.

Since CLKFB must be from CLK0 or CLK2X, the DLL output is used. Consequently, the minimum CLKIN frequency for the DPS function is 24 MHz.

Note: To ensure setup/hold time is calculated correctly, see (Xilinx Answer 18668).

Alternative Work-Around Using Variable Phase Shift

Configure the DCM with variable phase shift as follows:

1. Set the CLKOUT_PHASE_SHIFT attribute to VARIABLE.

2. Set the PHASE_SHIFT attribute to the required value. A positive value and phase shifting in the positive range is recommended. See (Xilinx Answer 15130).

3. Connect PSCLK to a clock signal.

4. Connect PSEN to GND if you do not intend to increment or decrement the phase shift.

5. Connect PSINCDEC to a signal, GND, or VCC.

Note: For best results, use 5.1i Service Pack 3 or later. The work-around causes MAP errors in earlier software versions, as described below:


ISE 4.1i

MAP reports the following error:

ERROR: MapLib:298 - PSINCDEC, PSEN, PSCLK and PSDONE of DCM symbol "<inst>" must be routed if CLKOUT_PHASE_SHIFT is set to variable.

To work around this, you can modify the HDL file so that PSINCDEC and PSEN are connected to a dummy input signal.


ISE 5.1i

The following error is reported:

5.1i: ERROR:LIT - PSINCDEC, PSEN, PSCLK and PSDONE of DCM symbol "inst_dcm_var_dcm_inst" (output signal=inst_dcm_var_clk0_buf) must be driven by active signals if CLKOUT_PHASE_SHIFT is set to VARIABLE.

You can safely ignore this error. To bypass this error in MAP, turn off the DRC check by using the following environment variable:

PC:

set XIL_MAP_SKIP_LOGICAL_DRC=1

UNIX:

setenv XIL_MAP_SKIP_LOGICAL_DRC


ISE 5.1i Service Pack 3

A fix in 5.1i Service Pack 3 prevents the MAP error from occurring. 5.1i Service Pack 3 is available at:

http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp

AR# 13349
Date Created 08/29/2007
Last Updated 07/01/2014
Status Active
Type General Article
Devices
  • Virtex-II