We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 14545

XC9500 - What variables affect the programming time of a 9500 device?


What variables affect the programming time of a device?


There is a difference between the programming algorithms for the XC9500 CPLD family and the XC9500XL/XC9500XV CPLD families.


Erase Pulse Time: 1.3 seconds

Program Pulse Time: 160 us (except XC9536, which uses 640 us)


Erase Pulse Time: 200 ms (was 100 ms in iMPACT 4.1i - 4.2isp2)

Program Pulse Time: 20 ms (was 10 ms in iMPACT 4.1i - 4.2isp2)

In addition, the results of the internal self-verify operation in these devices must be taken into consideration. The result of the self-verify can be "Success," "Failed," or "Not Completed." Both the erase and program operations include an internal self-verify operation.

During the RUNTEST wait time for programming, the device will program the word line; after this, the device will self-verify the word line programming results. The self-verify process begins immediately after the program operation stops. The program operation ends after one of the following two events:

1. When the boundary-scan tool waits in the RUNTEST state for a long enough period of time, the device's internal timer stops the program operation; typically, the self-verify operation completes while the device is still in the RUNTEST state.

2. When the boundary scan tool exits RUNTEST before the device's internal timer stops the program operation, the TAP state's transition out of the RUNTEST causes the program operation to stop.

The self-verify requires a finite time to complete; otherwise, a "Not Completed" result is captured. With Event #1, the self-verify usually completes within the RUNTEST state, so the self-verify result is always a "Success" or "Fail." (For information on the "retry" requirement when a "Fail" status is reported, please see the Xilinx Application Note "Using Serial Vector Format Files to Program XC9500 Devices In-System on Automatic Test Equipment and Third-Party Tools" (Xilinx XAPP067).)

In Event #2, the self-verify begins after the device leaves the RUNTEST state. Event #2 can be a problem because there is only a short time (depending on the TCK speed) before the TAP gets to the Capture-DR state in which it captures the operation results. If the self-verify does not complete within this time, the "Not Complete" status is captured for the operation results.

XC9500 family devices have particularly wide variations for internal timer accuracy. For some XC9500 devices, the internal timer may cause the operation to take longer than the RUNTEST time specified in the SVF file. This can lead to Event #2 above. At 1 MHz TCK, a failure is typically the result of the "Not Completed" status being captured.

The following work-arounds allow you to compensate for the XC9500 internal timer variation on ATE tools:

1. Slow down the TCK, which effectively increases the wait times for each RUNTEST statement in the SVF. Slowing of the TCK also delays the TAP transition time from the exit of the RUNTEST to the Capture-DR state; this gives the self-verify process time to complete.

2. Manually edit the SVF file and increase the RUNTEST numbers.

The RUNTEST times for the XC9500XL erase and all program operations appear to have plenty of margin for both the erase/program and self-verify operations to complete within the specified RUNTEST time.

The programming of a 9500 device will also be directly affected by the number of devices in the chain and by the frequency at which the part is being programmed.

AR# 14545
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article