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AR# 16425

7.1i PAR/TRACE LogiCORE PCI - "WARNING:Timing:2666 - Constraint ignored: TS_ADS_SETUP = MAXDELAY FROM TIMEGRP "PCI_PADS_D" TO TIMEGRP "SLOW_FFS" 4.350 ns"

Description

General Description:

When I run the PCI Core through PAR or TRACE, warnings similar to the following are displayed:

"WARNING:Timing:2666 - Constraint ignored: TS_ADS_SETUP =

MAXDELAY FROM TIMEGRP "PCI_PADS_D" TO TIMEGRP "SLOW_FFS" 4.350 nS ;"

"WARNING:Timing:2666 - Constraint ignored: TS_PAF_SETUP =

MAXDELAY FROM TIMEGRP "PCI_PADS_P" TO TIMEGRP "FAST_FFS" 4.350 nS ;"

"WARNING:Timing:2666 - Constraint ignored: TS_GNF_SETUP =

MAXDELAY FROM TIMEGRP "PCI_PADS_G" TO TIMEGRP "FAST_FFS" 6.350 nS ;"

"WARNING:Timing:2666 - Constraint ignored: TS_CNF_CKOUT =

MAXDELAY FROM TIMEGRP"FAST_FFS" TO TIMEGRP "PCI_PADS_C" 4.300 nS ;"

"WARNING:Timing:2666 - Constraint ignored: TS_GNF_CKOUT =

MAXDELAY FROM TIMEGRP "FAST_FFS" TO TIMEGRP "PCI_PADS_G" 4.300 nS ;"

"WARNING:Timing:2666 - Constraint ignored: TS_GNS_CKOUT =

MAXDELAY FROM TIMEGRP "SLOW_FFS" TO TIMEGRP "PCI_PADS_G" 4.300 nS ;"

"WARNING:Timing:2666 - Constraint ignored: TS_PAF_CKOUT =

MAXDELAY FROM TIMEGRP "FAST_FFS" TO TIMEGRP "PCI_PADS_P" 4.300 nS ;"

Solution

The constraints are expressed in a way such that a number of "empty" constraints exist. This means that the same path is covered by more than one constraint, so some of the constraints are unnecessary. The warnings above can be safely ignored.

Older versions of the Xilinx implementation software allowed this situation to pass without issuing warnings. Future UCF files will be updated to eliminate as many of these warnings as possible.

AR# 16425
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article