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AR# 18137

XST - "ERROR:HDLParsers:1401 - top_level.vhd Line 27. Object q of mode OUT cannot be read"

Description

Urgency: Standard

General Description:

Whenever I redirect an output signal back into my design, the error message listed below occurs during the syntax check (parsing):

entity top is

port

:

d ; in std_logic;

q1, q2 : out std_logic);

end entity;

:

:

q2 <= q1 and d;

Error Message

"ERROR:HDLParsers:1401 - top_level.vhd Line 27. Object q of mode OUT cannot be read."

I can perform this function in Verilog; how can I do this in VHDL?

Solution

In VHDL, when a signal has been declared as an output port, it cannot be used to drive other signals. There are four different types of modes for ports in VHDL:

in

out

inout

buffer

In Verilog, there are three modes:

input

output

inout

The mode type of buffer best corresponds to the mode type of the Verilog output. Because VHDL is a strongly typed language, Xilinx does not recommend using the mode type buffer because all of the ports that connect to this one buffer port must also be buffer ports. Instead you can create an intermediate signal that feeds back into the design, as well as drives the output port:

entity top is

port

:

d ; in std_logic;

q1, q2 : out std_logic);

end entity;

:

architecture top_arch of top is

signal q1_temp;

begin

:

:

q1 <= q1_temp;

q2 <= q1_temp and d;

AR# 18137
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article