We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21921

LogiCORE SPI-3 LINK Layer Core v4.0 - Release Notes and Known Issues for the SPI-3 Link Layer Core


General Description:

This Release Note is for the SPI-3 (POS-PHY L3) Link Layer v4.0 Core released in 7.1i IP Update 3 and contains the following:

- New Features

- Bug Fixes

- Known Issues

For the installation instructions and design tool requirements for 7.1i IP Update 3, see (Xilinx Answer 21938).


New Features in v4.0

Delivered through CORE Generator

Support added for ISE 7.1i

Support added for Spartan-3E

Standard LocalLink user interface for easy connectivity to LocalLink compliant interfaces

Support added for parameterizable internal FIFO

Support added for 8-bit and 16-bit data interfaces

Support added for Byte Level Transfer (DTPA/STPA signals)

Bug Fixes in v4.0

CR 171137: Changed default IOSTANDARD to 3.3V

Known Issues in 4.0

(Xilinx Answer 22027) PAR displays: "INFO:Par:62 - Your design did not meet timing."

(Xilinx Answer 22042) PAR places the clock pin and DCM on opposite sides of the chip, causing timing failures

(Xilinx Answer 22043) "ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design cannot be automatically placed."

(Xilinx Answer 22028) BitGen results in "ERROR:PhysDesignRules:755 - IOB comp <TX_DTPA(16)> at location <AH34> is VCCO"

(Xilinx Answer 22046) Spartan-3 and Spartan-3E designs need DCM phase shift

(Xilinx Answer 22052) When simulating design example, upper bit of TMOD is undefined

(Xilinx Answer 22053) When simulating design example, data might be sent to channels not used by the core

AR# 21921
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article