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AR# 21924

LogiCORE xFFT - Where can I find more information on scaling at each stage of the xFFT?

Description

Why can I not meet the data sheet timing numbers for Virtex-4 implementations of the xFFT?

Solution


It is important to remember that the FFT will scale the results.

Typically by 1/N (N = number of points). 
 
In the xFFT, the scaling is set by the user.  
 
The following is a supplement for the Scaling section of the datasheet, called Finite Word Length Considerations.
 
 
1. You need to choose an FFT radix. The xFFT supports either radix-4 or radix-2. 
 
 
2. Next you will need to determine the number of butterfly stages.
 
This is based on the number of points in the FFT.
 
- radix-4 - # of stages is log-base4(N) + 1 radix-2 stage at the output, for point sizes not divisible by 4 (N/4 != 0)

For example 512/4 != 0, 4 radix-4 stages and 1 radix-2 stage. 
 
- radix-2 = # of stages is log-base2(N) 
 
 
3. After you have the number of stages, you can calculate the scaling factor.

S = 2^((sum from i=0 to i=logN-1)*bi)
 
The notation might be confusing, but it is just a sum of the number of stages using the scaling value for each stage to get the overall scaling value S.
 
(Note: The equations are from the Scaling section of the datasheet, called Finite Word Length Considerations.)
 
This process states that we are going to do a binary shift by a certain number of bits in order to account for the scaling.

Since a shift by x bits equals a multiplication of 2^x, the equations are simply defining the number of bits that we shift for any given scaling schedule. 
 
 
Here is an example of this process for a 256 pt FFT:

1. We choose a radix-4 implementation. 
 
2. log-base4(256) = 4 stages 

e.g. log(256) / log(4) = 4 
 
3. If each stage is scaled by 2 , then we could calculate S by:

S = 2^(2 + 2 + 2 + 2) = 256.

Therefore the FFT output would be scaled by 1/256.
 

For more information, Please see the reference material mentioned at the end of the xFFT datasheet under the References section.
AR# 21924
Date Created 08/15/2005
Last Updated 03/06/2015
Status Active
Type General Article
Devices
  • FPGA Device Families