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AR# 22713

8.2 System Generator for DSP - When using Verilog as my target language with a DDS v4.0 or v5.0 in my design, error occurs: "ERROR:Xst:1370 - Line 6: Signal name clk not found in design."

Description

When using Verilog as my target language with a DDS v4.0 or v5.0 in my design, the following errors occur:

"ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.

ERROR:Xst:1341 - XCF parsing failed"

Solution

These errors occur because XST is changing the name of the net that System Generator attaches its constraints to in the XCF file. You can work around this by using the solution in (Xilinx Answer 18674) or by changing the target language to VHDL.

AR# 22713
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article