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AR# 23490

LogiCORE FIFO Generator v3.1 - Release Notes and Known Issues for the FIFO Generator Core (8.2i_IP1)


This Release Note is for the FIFO Generator 3.1 Core released in 8.2i IP Update 1 and contains the following:

- New Features

- Bug Fixes

- Known Issues

For installation instructions and design tools requirements, see (Xilinx Answer 23479).


New Features in v3.1

- Support added for Virtex-5

- Support added for ISE 8.2i

- Uses Block Memory Generator Core in block-memory-based implementations for more efficient block memory utilization in the Spartan-3, Virtex-II, Virtex-4, and Virtex-5 architectures

Bug Fixes in v3.1

(Xilinx Answer 22462) Incorrect status flag behavior issue in Virtex-4 FIFO16-based implementations. The fix supports FIFOs created using single FIFO16 primitive instantiations only.

Known Issues in v3.1

(Xilinx Answer 23691) Behavioral models are not supported for the built-in FIFO

(Xilinx Answer 23709) Map ERROR:LIT:250 - Pins WEA0, WEA1, WEA2, and WEA3 of RAMB16 symbol

(Xilinx Answer 20278) PROG_EMPTY and PROG_FULL can produce false-assertions

(Xilinx Answer 20291) Simulation Warning: "*/X_FF RECOVERY Low VIOLATION ON SET WITH RESPECT TO CLK"

(Xilinx Answer 20271) Simulation error on RESET: "Error: /proj/xbuilds/G.36/verilog/src/simprims/X_RAMB16.v(4289): $hold(..."

(Xilinx Answer 22014) When using FIFO Generator Core, the allowed data count width is less than it should be

(Xilinx Answer 22722) FIFO Generator Core now includes User Guide in addition to data sheet. Where can I find the User Guide for the FIFO Generator?

Device Issues

Please be aware of Virtex-5 Errata posted on http://www.xilinx.com/support/mysupport.htm
Fifo Generator core with Block Ram configuration is subject to all Block RAM issues listed in the errata.

AR# 23490
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article