LogiCORE CORDIC v3.0 - Why does the behavioral simulation for the CORDIC square root mode require 4 extra clocks after asserting the ND signal, before the data will be processed?
Description
Keywords: CORE Generator, CORDIC, square, root, reset, ND, input delay
Why does the behavioral simulation for the CORDIC require 4 extra clocks after asserting the ND signal, before the data will be processed?
When running a behavioral simulation of the CORDIC Core in the square root mode, the beginning and end of the input pulse are not calculated. There is about a 4-cycle delay (on top of the normal latency) from when ND is asserted to when valid data is presented on the output. Because of this delay, the first 4 data inputs and the last 4 data inputs are not calculated.
Solution
This is resolved in the CORDIC v4.0 and beyond.The solution is to use the Post-Translate simulation model.
For more information, see (Xilinx Answer 22333).
Please see (Xilinx Answer 29570) for a detailed list of LogiCORE CORDIC Release Notes and Known Issues.