We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24061

LogiCORE Block Memory Generator v2.2 - Unexpected data is seen on the output as the memory is generated with the wrong write mode


Regardless of whether the write mode is set to No Change or Write First, the behavior of the memory generated from the Block Memory Generator Core is still Read First. This issue occurs only when targeting Virtex-5 in Single Port RAM configuration and the RAMB36SDP_EXP primitive is used in the netlist.

This issue can result in output data mismatches between behavioral model and post-MAP simulations.


This issue is fixed in Block Memory Generator v2.3 which is delivered with ISE 8.2i IP Update #3.

Please install the latest IP Update and re-generate the latest core.

AR# 24061
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article