An Errata Item in the LXT and SXT ES Errata document (EN051 and EN052) describes the CRC Parallel Interface Timing. These Errata are faulty in two ways.
The figure below shows the work-around as tested by the Xilinx silicon characterization team. In the absence of the CRC Wizard v1.1, please implement the interface described in this figure.
To meet timing, the CRC flip-flops (FD1 in the figure) might have to be manually locked, or locked with an area group constraint. This Errata will not be necessary for production silicon.