An Errata Item in the LXT and SXT ES Errata document (EN051 and EN052) describes the CRC Parallel Interface Timing. These Errata are faulty in two ways.
1) The wording implies that both the CRCIN and CRCOUT data paths have a half-cycle clocking requirement. This is not the case. Only the CRCIN data path has this half-cycle requirement.
2) The Errata item states that the CRC Wizard implements the workaround. In fact, it did not implement this ES workaround until v1.1, in release in 9.1 IP3.
The figure below shows the workaround as tested by the Xilinx silicon characterization team. In the absence of the CRC Wizard v1.1, please implement the interface described in this figure. To meet timing, the CRC flip-flops (FD1 in the figure) may have to be manually locked, or locked with an area group constraint. This Errata will not be necessary for production silicon.