My design ignores the output of the block RAM at certain times. Do the setup and hold times of the ADDRESS inputs still need to be met, even if Write Enable (WE) is deasserted?
When a port is enabled, the setup and hold specifications of the ADDRESS inputs should never be violated, even if WE is deasserted.
For the Spartan-6 Generation (Spartan-6 LX, Spartan-6 LXT) and Spartan-3 Generation devices (Spartan-3, Spartan-3E, Spartan-3A, Spartan-3AN, and Spartan-3A DSP), when a block RAM port is enabled, all address transitions must meet the setup/hold time of the ADDR inputs with respect to the port clock. The setup and hold requirements for the block RAM inputs are listed in the device data sheet. The requirements must be met even when the read data output is ignored by the user and WE is deasserted. Otherwise, the block RAM contents might be unreliable.
There are some instances in which you might not be able to meet these requirements; for instance, if there is a multi-cycle path on the address input signals. Work around this by disabling the port via ENA/ENB during the time that the address inputs do not meet set up and hold requirements. De-asserting ENA/ENB disables the port so that violating the address input setup and hold requirements does not affect block RAM contents. Assert ENA/ENB again when resuming normal read/write functionality.
The Spartan-6 FPGA data sheet is located at:
The Spartan-3, Spartan-3E, Spartan-3A, Spartan-3AN, and Spartan-3A DSP FPGA Data Sheets are located at: