How do I estimate the power consumption of my Xilinx CPLD?
Please see the "Power Management" section on the front page of the density-specific data sheet, available at:
The Power Management section contains an equation that you can use to estimate power consumption.
The power dissipation in an XC9500 device is completely dependent on the pattern in the device and the state of its I/Os. The equation in the data sheet is only a rough estimate for the operating current in your device.
The following are sources of inaccuracy:
1. It assumes that your design has only one master clock operating at a frequency "f" and driving all the macrocells
2. There is no mention of combinatorial nodes which have no frequency
3. There is no mention of size of pterms (1 pterm with 2 inputs does not consume the same amount of power as 1 pterm with 20 inputs)
4. There is no mention of output loading
This equation should not be used as a definite projection of power consumption, but rather as an approximation.
These devices are supported by XPower, which is a power estimation program included with all Xilinx ISE products. XPower allows you to specify the signal toggle rates for your design, then uses this information to provide an accurate estimation of power consumption.
For other common CPLD questions, see the CPLD FAQ: (Xilinx Answer 24167) support for the CoolRunner-II family was added in software release 6.1i.