When I implement or synthesize a schematic design, the following message occurs:
"ERROR:DesignEntry:235 - net <net_name> is an illegal net name. It is a reserved word for <Verilog or VHDL>."
This is a valid error, and it occurs when a net name refers to a reserved word that is used by Verilog or VHDL. Before implementation, schematic sheets are netlisted to either Verilog or VHDL (depending on user preferences). Consequently, the netlister must check to prevent HDL keywords from being used as wire or instance names.
If you use "output" as a net name, the following error message occurs:
"ERROR:DesignEntry:235 - net "output" is an illegal net name. It is a reserved word for Verilog."
To remove this message, rename the net.
To ignore the keyword conflict (e.g., the reserved word is for Verilog and the netlist language is VHDL), follow these steps:
1. Select Edit -> Preferences -> Schematic Editor -> Check.
2. Uncheck the box next to "Check VHDL Reserved Keywords" or "Check Verilog Reserved Keywords" as appropriate.