LogiCORE Floating Point Operator (FPO) - Release Notes and Known Issues
Description
This Answer Record contains the Release Notes and Known Issues list for the CORE Generator LogiCORE Floating Point Operator.
The following information is listed for each version of the core:
- New Features
- Bug Fixes
- Known Issues
LogiCORE Floating Point Operator Lounge:
http://www.xilinx.com/products/ipcenter/FLOATING_PT.htm
Solution
General LogiCORE Floating Point Operator Issues- Software Support for the Virtex-6 Lower Power parts was added in this release but this IP is not yet supported and cannot be generated from the CORE Generator. To work around this issue, you can set your project to target an equivalent Virtex-6 LXT device, which allows you to generate a place holder IP that can be regenerated when support for the Virtex-6 low-power parts are added in the 11.3
LogiCORE Floating Point Operator v6.0
- Initial Release in ISE Design Suite 13.2
*To access these devices in the ISE Design Suite, contact your Xilinx FAE.
- Zynq-7000*
- Virtex-7
- Virtex-7 XT (7vx485t)
- Virtex-7 -2L
- Kintex-7
- Kintex-7 -2L
- Artix-7*
- Virtex-6 XC CXT/LXT/SXT/HXT
- Virtex-6 XQ LXT/SXT
- Virtex-6 -1L XC LXT/SXT
- Virtex-6 -1L XQ LXT/SXT
- Spartan-6 XC LX/LXT
- Spartan-6 XA LX/LXT
- Spartan-6 XQ LX/LXT
- Spartan-6 -1L XC LX
- Spartan-6 -1L XQ LX
- ISE 13.2 software support
- AXI4-Stream interfaces
- New operators:
- reciprocal: 1/x
- reciprocal square root: 1/sqrt(x)
- Bit-accurate C model
- N/A
- N/A
LogiCORE Floating Point Operator v5.0
- Initial Release in the 11.2 ISE Design Suite
- ISE 11.2 software support
- Virtex-6 and Spartan-6 support
- CR470172 Support for -u map option for all operators (for use with PlanAhead)
- All operators should now go through map with -u option specified.
- (Xilinx Answer 30806) Why does ISE 10.1 MAP fail, when the map -u options is used with the PlanAhead block-based implementation capability?
- CR470376 SCLR/CE priority clarification in data sheet
- The behavior that SCLR overrides CE is now also mentioned in the description of the SCLR port in Table 2.
- CR487995 Data sheet should clearly state that SCLR does not clear datapath
- The behavior that SCLR only resets control path is now explicitly mentioned in the description of the SCLR port in Table 2.
- CR470377 Data sheet documents HDL generics - this interface is no longer supported
- The only supported customer interface for core generation is through CORE Generator GUI. The description of the HDL generics has been removed from the data sheet.
- CR477962 Data sheet should be enhanced with numerical examples
- An example C-code program has been provided in the data sheet to enable customers to replicate core behavior at single precision with a desktop computer. This assumes that denormalized numbers are not used. This code can be used to generate hexadecimal values for comparison with an HDL simulation of the core.
- CR483358 SCLR should be greyed out in GUI when not applicable
- SCLR and CE are no longer available when latency is set to zero, as there is no clock port.
- CR481413 Data sheet has incorrect equation (page 2, bounds for fractional part)
- The lower bound for the fractional part (with hidden bit) is now correctly specified as 1. That is: 1 <= b0.b1...bp-1 < 2.
- N/A
LogiCORE Floating Point Operator v4.0
- Initial Release in ISE 10.1 IP Update 1
- Spartan-3A DSP support
- Increased speed of fabric and DSP48E based double precision adders on Virtex-5
- Latency and resources reductions for Virtex-5 single and double precision multipliers
- Increased range of multiplier usage options for Virtex-5 double precision multiplier
- Reduced latency compare and round operations
- CR443418: Behavior of denormalized numbers - Data sheet modified to explain in more detail how denormalized numbers are handled by the core.
- CR442822: Single precision adder failing timing on Virtex-5 - Enhancements in XST's BRAM inference support resulted in a fabric 6-input look-up-table being converted to BRAM. The associated routing to and from BRAM reduced operational frequency. The threshold at which BRAMs are used on Virtex-5 has been increased in 10.1, and so they are on longer inferred within this core. This XST fix will apply to v3.0 and v4.0 of the core.
- CR441538: NC-Sim warning - This simulation model has been modified in v4.0 to remove this warning. - Note that this warning will still be generated by v3.0 of the core.
- CR433981: Incorrect GUI popup message on page 3 - Fixed in version 4.0. - Latency field popup messages for when "Use Maximum Latency" ticked and unticked were swapped. These have been fixed.
- CR468257: MAP fails when -u option is used with environment variable XIL_MAP_NOCLIP_ON_ALL_SIGS_U set to 1 - Required by PlanAhead block-based implementation capability - Partially fixed in version 4.0. All add/subtract, DSP48/E/A based multiply, compare and float-to-float conversion operations can now be mapped in this way.
- (Xilinx Answer 30805) Why are the GUI Resource graph title and axes label so small?
- (Xilinx Answer 30806) Why does ISE 10.1 MAP fail, when the map -u options is used with the PlanAhead block-based implementation capability?
- (Xilinx Answer 31657) Why is the SCLR control pin being removed from my design?
LogiCORE Floating Point Operator v3.0
- Initial Release in ISE 8.2i IP Update 2 software
- Virtex-5 support, including:
- New option allows adder to make use of DSP48E in Virtex-5 or DSP48 in Virtex-4
- Multiplier now supports DSP48E
- Option to construct single precision multiplier from 1 DSP48E + logic
- Low latency adder architecture supported on Virtex-5 implementations
- Support for higher levels of pipelining in adder and multiplier for increased speed
- Improved size and speed of square root
- Conversion operations between floating-point types added
- Resource and speed estimation provided in customization GUI
- Support removed for Virtex and Spartan-2. Please use the v2.0 core if targeting these architectures
- CR 226251: Compare should have a result of 1-bit rather than use bit 0 of larger output
- (Xilinx Answer 24039) Why do I not see a resource estimation graph for my Floating Point operator function?
- (Xilinx Answer 25438) When I generate in ISE 9.2i, why can't I reach the 410 MHz performance listed for the Floating Point Adder in the data sheet?
- (Xilinx Answer 29597) When I generate in ISE 9.2i, why are the simulation results of my double precision floating point multiplier incorrect?
LogiCORE Floating Point Operator v2.0
- Initial Release in ISE 8.1i IP Update 1
- Support for conversion to and from fixed-point
- Greater choice of word length
- User-specifiable latency
- Level of hardware reuse for divide and square-root can be specified
- Support for clock enable
- CR 213669: Data sheet does not contain timing information
- CR 214410: GUI must have dynamic format diagram
- N/A
LogiCORE Floating Point Operator v1.0 r1
- Initial Release in ISE 7.1i IP Update 2
- N/A
- CR 209982: Data sheet modified to explain how a Verilog simulation model can be generated for the core.
- N/A
LogiCORE Floating Point Operator v1.0
- Initial Release in ISE 7.1i IP Update 1
- First release
- IEEE-754-compliant floating-point operators with only minor documented deviations
- Can be configured for high-speed operation with an instruction issued on every clock cycle
- Supports add/subtract, multiply, divide and square-root operations, with a range of standard and nonstandard sizes, including single and double precision
- Support for Virtex-4 DSP48 feature
- Includes multi-cycle divide and compare operations for single precision
- VHDL behavioral model
- Core can be generated directly from a VHDL instantiation with XST transparently calling CORE Generator
- N/A
- N/A
Applies To
IP
- Floating-Point Operators