UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29689

Virtex-5 Integrated Block for PCI Express - What are the LTSSM timeout values in simulation?

Description

What are the LTSSM timeout values in simulation?

Solution

The LTSSM (Link Training and Status State Machine) contains multiple millisecond timeouts as it cycles through the states. These timeout values are decreased during simulation to make the timer values more reasonable. The value is dependent upon an attribute on the simulation model called "TEST_MODE." Figure 1 shows the values of the internal LTSSM timers when "TEST_MODE =1" and "TEST_MODE = 0".

Figure 1. Internal LTSSM timer values when TEST_MODE = 0/1
Figure 1. Internal LTSSM timer values when TEST_MODE = 0/1

The smartmodel for PCI Express has TEST_MODE =1.

NOTE: Users cannot set TEST_MODE to "1" for hardware implementation. It is automatically set to "0", otherwise the block would not be able to train with the link partner device.

AR# 29689
Date Created 11/03/2007
Last Updated 12/15/2012
Status Active
Type General Article