Keyword: MPMC v3, data width, DDR, SDRAM
I am using the SDRAM part MT48LC4M32B2-6 that has a data width of 32. When I run my design through PlatGen, the C_MEM_PART_DATA_WIDTH parameter is updated to 32, which is out of range of the allowable values (8, 16).
I checked the MPMC User Guide and the 32-bit data width is supported (64-bit, as well). Why is the data width in MPMC limited to 8 and 16 only? How do I resolve this error?
To work around this issue, create a custom memory that has the same timing, but a component width (C_MEM_PART_DATA_WIDTH) of x16. Next, set the total memory width (C_MEM_DATA_WIDTH) to 32.