We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30451

9.2.04i iMPACT - Verify fails if there is data in the PROM


Verification of FPGA after successful configuration from PROM results in verification failure if data remains in the PROM.

Example of the error generated in iMPACT:

"ERROR:Bitstream:98 - There are xxxxx differences.

ERROR:iMPACT:395 - The number of difference is xxxxx."

The number of differences varies each time.


The error occurs only if there is data in the PROM. The problem stems from the CCLK signal starting up when verification is attempted and data from the PROM is clocked into the FPGA, which causes verification to fail.

Programming the PROM, configuring the FPGA from the PROM, and subsequent erasure of the PROM before FPGA verification results in successful verification of the FPGA each time.

Starting with iMPACT 11.1, the Verify algorithm changes to prevent this occurring for Spartan-3A and Virtex-5 devices. This change means that BRAM data are longer Verified.

AR# 30451
Date Created 03/05/2008
Last Updated 12/15/2012
Status Active
Type General Article