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AR# 30626

IP-DSP - Why are there mismatches between the behavioral simulation and the post-translate simulation when using ISE Simulator, NC-Sim with the CIC Compiler, DDS Compiler, or the Sine CoSine LUT IP?

Description

Why are there mismatches between the behavioral simulation and the post-translate simulation, when using ISE Simulator, NC-Sim with the CIC Compiler, DDS Compiler, or the Sine CoSine LUT IP?

Also, why do these mismatches not occur when I use ModelSim?

Solution

This issue is caused by a float to integer conversion function that is used in the behavioral model for the following list of cores. The IEEE standard for this function can be interpreted in multiple ways. Consequently, there are differences in how the rounding is performed, depending on which simulator is used. These cores work as expected in ModelSim, but not in ISE Simulator or NC-Sim.

CIC Compiler v1.0

DDS Compiler v1.1

DDS Compiler v2.0

Sine CoSine Look Up Table (Sin Cos LUT) v4.0

Sine CoSine Look Up Table (Sin Cos LUT) v4.1

Sine CoSine Look Up Table (Sin Cos LUT) v4.2

Sine CoSine Look Up Table (Sin Cos LUT) v5.0

See (Xilinx Answer 29297) for a detailed list of LogiCORE Cascaded Integrator Comb Compiler (CIC Compiler) Release Notes and Known Issues.

See (Xilinx Answer 29976) for a detailed list of LogiCORE Direct Digital Synthesizer Compiler (DDS Compiler) Release Notes and Known Issues.

See (Xilinx Answer 30162) for a detailed list of LogiCORE Sine-Cosine Look-Up Table (Sin Cos LUT) Release Notes and Known Issues.

AR# 30626
Date Created 03/28/2008
Last Updated 12/15/2012
Status Active
Type General Article