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AR# 30696

10.1 EDK, XPS LL TEMAC v1.01a - My design with SGMII did not work (stay in Reset state)

Description

My design is targeting a Virtex-4 FX and uses the EMAC IP "xps_ll_temac" in SGMII Mode.

It is not possible to read with the PPC the internal registers of the TEMAC. What I found out is that the TEMAC is held at reset. This means that the GT11 transmitter logic is not working properly. The MGT_CLKs (P/N) are connected with a diff. 125MHZ clock.

Solution

The Virtex-4 SGMII requires a 250 MHz clock to guarantee operation, because of jitter problems with Virtex-4 MGTs. The data sheet will be updated to reflect that the clock should be 250 MHz for Virtex-4 and 125 MHz for V5.

If only a 125 MHz clock source is available, please add the following constraints to the system.ucf file to change the MGTs. Note that the Virtex-4 MGTs are not guaranteed to fully work, because of jitter issues when using 125 MHz rather than 250 MHz clock.

INST */GT11_DUAL_1000X_inst/GT11_1000X_B RXPLLNDIVSEL = 20; # changed from 10 because ML405 has only a 125 MHz clock for SFP instead of 250 MHz

INST */GT11_DUAL_1000X_inst/GT11_1000X_B TXPLLNDIVSEL = 20; # changed from 10 because ML405 has only a 125 MHz clock for SFP instead of 250 MHz

INST */GT11_DUAL_1000X_inst/GT11_1000X_A RXPLLNDIVSEL = 20; # changed from 10 because ML405 has only a 125 MHz clock for SFP instead of 250 MHz

INST */GT11_DUAL_1000X_inst/GT11_1000X_A TXPLLNDIVSEL = 20; # changed from 10 because ML405 has only a 125 MHz clock for SFP instead of 250 MHz

This will also be included in the v1.01b of the XPS LL TEMAC core data sheet.

AR# 30696
Date Created 05/19/2008
Last Updated 12/15/2012
Status Active
Type General Article