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AR# 30812

10.1 UniSim - DCM_SP does not lock in VHDL simulation


DCM_SP does not lock in VHDL simulation. Why?


DCM_SP locked signal is not connected in VHDL. This is a bug in the model, and it is fixed in 10.1 Sp2.

If you want a immediate fix for this model, please open a Technical Support WebCase: http://www.xilinx.com/support/clearexpress/websupport.htm

This issue is not seen by Verilog models.

AR# 30812
Date 12/15/2012
Status Active
Type General Article
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