DCM_SP does not lock in VHDL simulation. Why?
DCM_SP locked signal is not connected in VHDL. This is a bug in the model, and it is fixed in 10.1 Sp2.
If you want a immediate fix for this model, please open a Technical Support WebCase: http://www.xilinx.com/support/clearexpress/websupport.htm
This issue is not seen by Verilog models.