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AR# 30933

10.1 EDK, MPMC v4.01.a - DM-Pins always High and DQ incorrect on writes when using SDR SDRAM PHY

Description

Keywords: MPMC4, MPMC3, Data, mask, SDRAM, corrupt, invalid

In cases of SDRAM-Interface and tRCD-Timing being lower than the period of the clock, the DM-Pins of the SDRAM-Interfaces are always High, and incorrect data is presented to the DQ data bus.

In simulation, a memory model note similar to the following could occur, where data is never actually written to memory:

# system_tb.mem : at time 121810.0 ns WRITE: Bank = 0 Row = 0, Col = 31, Data = Hi-Z due to DQM
# system_tb.mem : at time 121840.0 ns WRITE: Bank = 0 Row = 0, Col = 28, Data = Hi-Z due to DQM
# system_tb.mem : at time 121870.0 ns WRITE: Bank = 0 Row = 0, Col = 29, Data = Hi-Z due to DQM
# system_tb.mem : at time 121900.0 ns WRITE: Bank = 0 Row = 0, Col = 30, Data = Hi-Z due to DQM

Solution

To work around this issue, increase the MPMC tRCD timing parameter, C_MEM_PART_TRCD, to be greater than the memory clock period, C_MPMC_CLK0_PERIOD_PS.

PARAMETER C_MPMC_CLK0_PERIOD_PS = 30000
PARAMETER C_MEM_PART_TRCD = 35000

This issue is to be fixed starting with MPMC v4.03.a, to be released in EDK 10.1, Service Pack 3.
AR# 30933
Date Created 07/21/2008
Last Updated 09/04/2008
Status Active
Type General Article